Issued Patents All Time
Showing 26–50 of 146 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9417804 | System and method for memory block pool wear leveling | Alessia Marelli, Luca Crippa | 2016-08-16 |
| 9397701 | System and method for lifetime specific LDPC decoding | Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie | 2016-07-19 |
| 9305661 | Nonvolatile memory system that uses programming time to reduce bit errors | Luca Crippa | 2016-04-05 |
| 9235467 | System and method with reference voltage partitioning for low density parity check decoding | Alessia Marelli, Peter Z. Onufryk | 2016-01-12 |
| 9128858 | Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values | Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser | 2015-09-08 |
| 9092353 | Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system | Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser | 2015-07-28 |
| 8990661 | Layer specific attenuation factor LDPC decoder | Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie | 2015-03-24 |
| 8971112 | Method of programming a multi-level memory device | Luca Crippa | 2015-03-03 |
| 8966335 | Method for performing error corrections of digital information codified as a symbol sequence | Massimiliano Lunelli, Roberto Ravasio, Alessia Marelli | 2015-02-24 |
| 8707122 | Nonvolatile memory controller with two-stage error correction technique for enhanced reliability | Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie | 2014-04-22 |
| 8694855 | Error correction code technique for improving read stress endurance | Luca Crippa, Alessia Marelli | 2014-04-08 |
| 8694849 | Shuffler error correction code system and method | Alessia Marelli, Peter Z. Onufryk | 2014-04-08 |
| 8656257 | Nonvolatile memory controller with concatenated error correction codes | Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie | 2014-02-18 |
| 8621318 | Nonvolatile memory controller with error detection for concatenated error correction codes | Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie | 2013-12-31 |
| 8572361 | Configuration of a multilevel flash memory device | Angelo Bovino, Roberto Ravasio | 2013-10-29 |
| 8553462 | Method of programming a multi-level memory device | Luca Crippa | 2013-10-08 |
| 8397144 | BCH data correction system and method | Christopher I. W. Norrie, Alessia Marelli, Peter Z. Onufryk | 2013-03-12 |
| 8347201 | Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code | Alessia Marelli, Valeria Intini, Roberto Ravasio | 2013-01-01 |
| 8065467 | Non-volatile, electrically-programmable memory | Roberto Ravasio | 2011-11-22 |
| 7937576 | Configuration of a multi-level flash memory device | Angelo Bovino, Roberto Ravasio | 2011-05-03 |
| 7908543 | Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code | Alessia Marelli, Valeria Intini, Roberto Ravasio | 2011-03-15 |
| 7889586 | Circuit and method for retrieving data stored in semiconductor memory cells | Luca Crippa, Giancarlo Ragone, Miriam Sangalli | 2011-02-15 |
| 7863967 | Multistage regulator for charge-pump boosted voltage applications | Luca Crippa, Miriam Sangalli, Giancarlo Ragone | 2011-01-04 |
| 7777466 | Voltage regulator or non-volatile memories implemented with low-voltage transistors | Luca Crippa, Giancarlo Ragone, Miriam Sangalli, Giovanni Campardo | 2010-08-17 |
| 7730357 | Integrated memory system | Roberto Ravasio | 2010-06-01 |