Issued Patents All Time
Showing 51–75 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7502058 | Imager with tuned color filter | William M. Hiatt, Ulrich Boettiger | 2009-03-10 |
| 7485836 | Row driver for selectively supplying operating power to imager pixel | Peter P. Altice, Jr., Jeffrey D. Bruce, Joey Shah, Richard A. Mauritzson | 2009-02-03 |
| 7468532 | Method and apparatus providing capacitor on an electrode of an imager photosensor | — | 2008-12-23 |
| 7465602 | Anti-blooming storage pixel | Peter P. Altice, Jr. | 2008-12-16 |
| 7449736 | Pixel with transfer gate with no isolation edge | — | 2008-11-11 |
| 7446357 | Split trunk pixel layout | — | 2008-11-04 |
| 7443437 | Image sensor with a gated storage node linked to transfer gate | Peter P. Altice, Jr. | 2008-10-28 |
| 7432540 | Dual conversion gain gate and capacitor combination | — | 2008-10-07 |
| 7332786 | Anti-blooming storage pixel | Peter P. Altice, Jr. | 2008-02-19 |
| 7324690 | Metal mask for light intensity determination and ADC calibration | Peter P. Altice, Jr., Grzegorz M. Waligorski | 2008-01-29 |
| 7244918 | Method and apparatus providing a two-way shared storage gate on a four-way shared pixel | Joey Shah | 2007-07-17 |
| 7176109 | Method for forming raised structures by controlled selective epitaxial growth of facet using spacer | Er-Xuan Ping | 2007-02-13 |
| 7157324 | Transistor structure having reduced transistor leakage attributes | Vishnu K. Agarwal, Fred Fishburn, Rongsheng Yang, Howard E. Rhodes | 2007-01-02 |
| 7105899 | Transistor structure having reduced transistor leakage attributes | Vishnu K. Agarwal, Fred Fishburn, Rongsheng Yang, Howard E. Rhodes | 2006-09-12 |
| 6650564 | System and method for enabling chip level erasing and writing for magnetic random access memory devices | Ren Earl | 2003-11-18 |
| 6569733 | Gate device with raised channel and method | — | 2003-05-27 |
| 6569734 | Method for two-sided fabrication of a memory array | — | 2003-05-27 |
| 6528888 | Integrated circuit and method | Chih-Chen Cho, William R. McKee, Isamu Asano, Robert Tsu | 2003-03-04 |
| 6522577 | System and method for enabling chip level erasing and writing for magnetic random access memory devices | Ren Earl | 2003-02-18 |
| 6423596 | Method for two-sided fabrication of a memory array | — | 2002-07-23 |
| 6417091 | Mask and method for forming dynamic random access memory (DRAM) contacts | Michael Keleher, Troy H. Herndon, Jing Shu | 2002-07-09 |
| 6330181 | Method of forming a gate device with raised channel | — | 2001-12-11 |
| 6300179 | Gate device with access channel formed in discrete post and method | — | 2001-10-09 |
| 6290808 | Chemical mechanical polishing machine with ultrasonic vibration and method | Ming-Jang Hwang, Chih-Chen Cho | 2001-09-18 |
| 6218311 | Post-etch treatment of a semiconductor device | Ming-Jang Hwang, Chih-Chen Cho, William R. McKee | 2001-04-17 |