Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6770954 | Semiconductor device with SI-GE layer-containing low resistance, tunable contact | John Walsh | 2004-08-03 |
| 6759335 | Buried strap formation method for sub-150 nm best DRAM devices | — | 2004-07-06 |
| 6737316 | Method of forming a deep trench DRAM cell | — | 2004-05-18 |
| 6703279 | Semiconductor device having contact of Si-Ge combined with cobalt silicide | — | 2004-03-09 |
| 6566190 | Vertical internally-connected trench cell (V-ICTC) and formation method for semiconductor memory devices | John Walsh | 2003-05-20 |
| 6562714 | Consolidation method of junction contact etch for below 150 nanometer deep trench-based DRAM devices | — | 2003-05-13 |
| 6544888 | Advanced contact integration scheme for deep-sub-150 nm devices | — | 2003-04-08 |
| 6528367 | Self-aligned active array along the length direction to form un-biased buried strap formation for sub-150 NM BEST DRAM devices | — | 2003-03-04 |
| 6521956 | Semiconductor device having contact of Si-Ge combined with cobalt silicide | — | 2003-02-18 |
| 6511905 | Semiconductor device with Si-Ge layer-containing low resistance, tunable contact | John Walsh | 2003-01-28 |
| 6475859 | Plasma doping for DRAM with deep trenches and hemispherical grains | Helmut Tews, Joachim Hoepfner | 2002-11-05 |
| 6475906 | Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices | — | 2002-11-05 |
| 6472302 | Integration method for raised contact formation for sub-150 nm devices | — | 2002-10-29 |
| 6426253 | Method of forming a vertically oriented device in an integrated circuit | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Stephan Kudelka | 2002-07-30 |
| 6372567 | Control of oxide thickness in vertical transistor structures | Helmut Tews, Ulrike Gruening | 2002-04-16 |
| 6362040 | Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates | Helmut Tews, Ulrike Gruening, Raj Jammy, John Faltermeier | 2002-03-26 |
| 6348388 | Process for fabricating a uniform gate oxide of a vertical transistor | Johnathan E. Faltermeier, Ulrike Gruening, Suryanarayan G. Hegde, Rajarao Jammy, Helmut Tews | 2002-02-19 |
| 6335247 | Integrated circuit vertical trench device and method of forming thereof | Helmut Tews, Alexander Michaelis, Stephan Kudelka, Uwe Schroeder | 2002-01-01 |
| 6284666 | Method of reducing RIE lag for deep trench silicon etching | Munir D. Naeem, Gangadhara S. Mathad, Byeong Y. Kim, Stephan Kudelka, Heon Lee +3 more | 2001-09-04 |
| 6207573 | Differential trench open process | — | 2001-03-27 |
| 6159874 | Method of forming a hemispherical grained capacitor | Helmut Tews | 2000-12-12 |
| 6150670 | Process for fabricating a uniform gate oxide of a vertical transistor | Johnathan E. Faltermeier, Ulrike Gruening, Suryanarayan G. Hegde, Rajarao Jammy, Helmut Tews | 2000-11-21 |