Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7786015 | Method for fabricating self-aligned complementary pillar structures and wiring | Yung-Tin Chen, Chun-Ming Wang, Christopher J. Petti, Steven Maxwell | 2010-08-31 |
| 7759201 | Method for fabricating pitch-doubling pillar structures | Christopher J. Petti | 2010-07-20 |
| 7754605 | Ultrashallow semiconductor contact by outdiffusion from a solid source | S. Brad Herner | 2010-07-13 |
| 7732235 | Method for fabricating high density pillar structures by double patterning using positive photoresist | Roy E. Scheuerlein | 2010-06-08 |
| 7718546 | Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon | Michael Konevecki | 2010-05-18 |
| 7682942 | Method for reducing pillar structure dimensions of a semiconductor device | Yung-Tin Chen, Michael Chan, Paul Wai Kie Poon | 2010-03-23 |
| 7575984 | Conductive hard mask to protect patterned features during trench etch | Usha Raghuram, Samuel V. Dunton, Michael Konevecki | 2009-08-18 |
| 7560339 | Nonvolatile memory cell comprising a reduced height vertical diode | S. Brad Herner | 2009-07-14 |
| 7553611 | Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure | Yung-Tin Chen, Christopher J. Petti, Tanmay Kumar | 2009-06-30 |
| 7300876 | Method for cleaning slurry particles from a surface polished by chemical mechanical polishing | Samuel V. Dunton | 2007-11-27 |
| 7285464 | Nonvolatile memory cell comprising a reduced height vertical diode | S. Brad Herner | 2007-10-23 |
| 7018878 | Metal structures for integrated circuits and methods for making the same | Michael A. Vyvoda, K. Leo Zhang | 2006-03-28 |
| 6734620 | Structure, fabrication, and corrective test of electron-emitting device having electrode configured to reduce cross-over capacitance and/or facilitate short-circuit repair | Matthew A. Bonn, Hidenori Kemmotsu, Theodore S. Fahlen | 2004-05-11 |
| 4289574 | Process for patterning metal connections on a semiconductor structure by using an aluminum oxide etch resistant layer | Robert Berry | 1981-09-15 |