Issued Patents All Time
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9735898 | Communication channel calibration using feedback | Jun Kim, Glenn Chiu | 2017-08-15 |
| 9652176 | Memory controller for micro-threaded memory operations | Frederick A. Ware, Craig E. Hampel, Chad A. Bellows, Lawrence Lai | 2017-05-16 |
| 9568942 | Drift adjustment in timing signal forwarded from memory controller to memory device based on a detected phase delay occurring on a second timing signal with a different frequency | Jun Kim, Pak Shing Chau | 2017-02-14 |
| 9564885 | Event-driven clock duty cycle control | Pak Shing Chau, Jun Kim | 2017-02-07 |
| 9502096 | Protocol for memory power-mode control | Wayne F. Ellis, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2016-11-22 |
| 9292223 | Micro-threaded memory | Frederick A. Ware, Craig E. Hampel, Chad A. Bellows, Lawrence Lai | 2016-03-22 |
| 9235537 | Drift detection in timing signal forwarded from memory controller to memory device | Jun Kim, Pak Shing Chau | 2016-01-12 |
| 9172521 | Communication channel calibration using feedback | Jun Kim, Glenn Chiu | 2015-10-27 |
| 9129666 | Robust commands for timing calibration or recalibration | Wayne F. Ellis, Yohan U. Frans, Lawrence Lai | 2015-09-08 |
| 9117496 | Memory device comprising programmable command-and-address and/or data interfaces | Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Akash Bansal +2 more | 2015-08-25 |
| 9111645 | Request-command encoding for reduced-data-rate testing | Kishore Ven Kasamsetty, Kurt Knorpp, Frederick A. Ware | 2015-08-18 |
| 8942056 | Protocol for memory power-mode control | Wayne F. Ellis, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty | 2015-01-27 |
| 8908466 | Multi-column addressing mode memory system including an integrated circuit memory device | Frederick A. Ware, Lawrence Lai, Chad A. Bellows | 2014-12-09 |
| 8595459 | Micro-threaded memory | Frederick A. Ware, Craig E. Hampel, Chad A. Bellows, Lawrence Lai | 2013-11-26 |
| 8432766 | Multi-column addressing mode memory system including an integrated circuit memory device | Frederick A. Ware, Lawrence Lai, Chad A. Bellows | 2013-04-30 |
| 8391099 | Integrated circuit memory device, system and method having interleaved row and column control | Kishore Ven Kasamsetty, Lawrence Lai | 2013-03-05 |
| 8190808 | Memory device having staggered memory operations | Lawrence Lai, Chad A. Bellows | 2012-05-29 |
| 8154947 | Multi-column addressing mode memory system including an integrated circuit memory device | Frederick A. Ware, Lawrence Lai, Chad A. Bellows | 2012-04-10 |
| 8121803 | Communication channel calibration using feedback | Jun Kim, Glenn Chiu | 2012-02-21 |
| 8096812 | Chip socket assembly and chip file assembly for semiconductor chips | Donald V. Perino, John B. Dillon | 2012-01-17 |
| 8050134 | Multi-column addressing mode memory system including an integrated circuit memory device | Frederick A. Ware, Lawrence Lai, Chad A. Bellows | 2011-11-01 |
| 7940598 | Integrated circuit memory device, system and method having interleaved row and column control | Kishore Ven Kasamsetty, Lawrence Lai | 2011-05-10 |
| 7907470 | Multi-column addressing mode memory system including an integrated circuit memory device | Frederick A. Ware, Lawrence Lai, Chad A. Bellows | 2011-03-15 |
| 7755968 | Integrated circuit memory device having dynamic memory bank count and page size | Steven C. Woo, Michael Ching, Chad A. Bellows, Kurt Knorpp, Jun Kim | 2010-07-13 |
| 7516029 | Communication channel calibration using feedback | Jun Kim, Glenn Chiu | 2009-04-07 |