Issued Patents All Time
Showing 76–100 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7240254 | Multiple power levels for a chip within a multi-chip semiconductor package | — | 2007-07-03 |
| 7157940 | System and methods for a high-speed dynamic data bus | — | 2007-01-02 |
| 7139945 | Chip testing within a multi-chip semiconductor package | — | 2006-11-21 |
| 7133798 | Monitoring signals between two integrated circuit devices within a single package | — | 2006-11-07 |
| 7103815 | Testing of integrated circuit devices | Fan Ho | 2006-09-05 |
| 7061263 | Layout and use of bond pads and probe pads for testing of integrated circuits devices | — | 2006-06-13 |
| 7006940 | Set up for a first integrated circuit chip to allow for testing of a co-packaged second integrated circuit chip | — | 2006-02-28 |
| 6996652 | High-speed segmented data bus architecture | — | 2006-02-07 |
| 6983404 | Method and apparatus for checking the resistance of programmable elements | Douglas J. Cutter, Fan Ho, Kurt D. Beigel, Brett Debenham, Dien Luong +2 more | 2006-01-03 |
| 6882171 | Bonding pads for testing of a semiconductor device | — | 2005-04-19 |
| 6812726 | Entering test mode and accessing of a packaged semiconductor device | — | 2004-11-02 |
| 6754866 | Testing of integrated circuit devices | Fan Ho | 2004-06-22 |
| 6732304 | Chip testing within a multi-chip semiconductor package | — | 2004-05-04 |
| 6657914 | Configurable addressing for multiple chips in a package | Fan Ho | 2003-12-02 |
| 6365421 | Method and apparatus for storage of test results within an integrated circuit | Brett Debenham, Kim Pierce, Douglas J. Cutter, Kurt D. Beigel, Fan Ho +6 more | 2002-04-02 |
| 6208568 | Circuit for cancelling and replacing redundant elements | Paul S. Zagar | 2001-03-27 |
| 6194738 | Method and apparatus for storage of test results within an integrated circuit | Brett Debenham, Kim Pierce, Douglas J. Cutter, Kurt D. Beigel, Fan Ho +6 more | 2001-02-27 |
| 6188594 | Reduced-pitch 6-transistor NMOS content-addressable-memory cell | — | 2001-02-13 |
| 6185705 | Method and apparatus for checking the resistance of programmable elements | Douglas J. Cutter, Fan Ho, Kurt D. Beigel, Brett Debenham, Dien Luong +2 more | 2001-02-06 |
| 6166976 | Multiple equilibration circuits for a single bit line | — | 2000-12-26 |
| 6154386 | Memory device having a wide data path | — | 2000-11-28 |
| 6154410 | Method and apparatus for reducing antifuse programming time | Douglas J. Cutter, Kurt D. Beigel, Fan Ho, Patrick J. Mullarkey, Dien Luong +2 more | 2000-11-28 |
| 6104645 | High speed global row redundancy system | Paul S. Zagar | 2000-08-15 |
| RE36821 | Wordline driver circuit having a directly gated pull-down device | Stephen L. Casper, Paul S. Zagar | 2000-08-15 |
| 6097647 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Paul S. Zagar, Brent Keeth | 2000-08-01 |