Issued Patents All Time
Showing 101–125 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6078513 | NMOS dynamic content-addressable-memory CAM cell with self-booting pass transistors and local row and column select | Deepraj S. Puar | 2000-06-20 |
| 6033945 | Multiple equilibration circuits for a single bit line | — | 2000-03-07 |
| 6031784 | Hierarchical decoding of a memory device | — | 2000-02-29 |
| 5999480 | Dynamic random-access memory having a hierarchical data path | Paul S. Zagar, Troy A. Manning, Brent Keeth, Ken Waller | 1999-12-07 |
| 5970008 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Paul S. Zagar, Brent Keeth | 1999-10-19 |
| 5970020 | Controlling the set up of a memory address | — | 1999-10-19 |
| 5919269 | Supervoltage detection circuit having a multi-level reference voltage | — | 1999-07-06 |
| 5912579 | Circuit for cancelling and replacing redundant elements | Paul S. Zagar | 1999-06-15 |
| 5901105 | Dynamic random access memory having decoding circuitry for partial memory blocks | Paul S. Zagar, Troy A. Manning, Brent Keeth, Ken Waller | 1999-05-04 |
| 5850368 | Burst EDO memory address counter | Paul S. Zagar, Brett Williams, Troy A. Manning | 1998-12-15 |
| 5838620 | Circuit for cancelling and replacing redundant elements | Paul S. Zagar | 1998-11-17 |
| 5798970 | Memory device output buffer | — | 1998-08-25 |
| 5761145 | Efficient method for obtaining usable parts from a partially good memory integrated circuit | Paul S. Zagar, Brent Keeth | 1998-06-02 |
| 5745499 | Supervoltage detection circuit having a multi-level reference voltage | — | 1998-04-28 |
| RE35750 | Wordline driver circuit having an automatic precharge circuit | Stephen L. Casper, Paul S. Zagar | 1998-03-24 |
| 5706238 | Self current limiting antifuse circuit | Douglas J. Cutter, Kurt D. Beigel, Fan Ho, Patrick J. Mullarkey, Dien Luong +2 more | 1998-01-06 |
| 5677884 | Circuit for cancelling and replacing redundant elements | Paul S. Zagar | 1997-10-14 |
| 5675549 | Burst EDO memory device address counter | Paul S. Zagar, Brett L. Wiliams, Troy A. Manning | 1997-10-07 |
| 5631862 | Self current limiting antifuse circuit | Douglas J. Cutter, Kurt D. Beigel, Fan Ho, Patrick J. Mullarkey, Dien Luong +2 more | 1997-05-20 |
| 5614859 | Two stage voltage level translator | — | 1997-03-25 |
| 5602783 | Memory device output buffer | — | 1997-02-11 |
| 5528539 | High speed global row redundancy system | Paul S. Zagar | 1996-06-18 |
| 5488583 | Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits | William K. Waller, Paul S. Zagar | 1996-01-30 |
| 5465232 | Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory | Paul S. Zagar | 1995-11-07 |
| 5311481 | Wordline driver circuit having a directly gated pull-down device | Stephen L. Casper, Paul S. Zagar | 1994-05-10 |