Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of fabricating memory device with spaced-apart semiconductor charge storage regions

Methods of fabricating memory device with spaced-apart semiconductor charge storage regions

US Patent 9793288 · Granted Oct 17, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Three-dimensional memory device with laterally separated source select electrode2025
Select gate bias gradation structure in NAND memory2025
Sub-block separation in NAND memory through word line based selectors2025
Method for producing hollow silica particles2024
Three-dimensional memory device containing a pillar contact between channel and 2024
Three-dimensional memory device containing self-aligned bit line contacts and me2024
Three-dimensional memory device with separated source-side lines and method of m2024
Lateral transistors for selecting blocks in a three-dimensional memory array and2024
Three dimensional memory device containing truncated channels and method of oper2023
Lateral transistors for selecting blocks in a three-dimensional memory array and2023
Method for producing hollow silica particles2023
Three-dimensional memory device and method of erasing thereof from a source side2022