Assignee
Inventors
- Raymond Cheung Yeung (18 patents)
- Irfan Waheed (2 patents)
- Mark H. Nodine (8 patents)
{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method for preparing for and formally verifying a modified integrated circuit design", "item": "https://www.patentleaderboard.com/patent/8429580"}]}
Skip to contentUS Patent 8429580 · Granted Apr 23, 2013