{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design", "item": "https://www.patentleaderboard.com/patent/7956636"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design

Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design

US Patent 7956636 · Granted Jun 7, 2011

Estimated economic value: $79,349,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Generating test benches for pre-silicon validation of retimed complex IC designs2015
Method for piecewise hierarchical sequential verification2013
Method for preparing re-architected designs for sequential equivalence checking2013
Method for preparing for and formally verifying a modified integrated circuit de2013
Generating test benches for pre-silicon validation of retimed complex IC designs2012
Circuit design verification tool and method therefor using maxwell's equations2000
Method for verifying protocol conformance of an electrical interface1999