| 9053265 |
Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design |
— |
2015-06-09 |
| 8448107 |
Method for piecewise hierarchical sequential verification |
Nathan Francis Sheeley, Nicolas X. Pena, Irfan Waheed, Patrick Peters, Adrian Isles |
2013-05-21 |
| 8443319 |
Method for preparing re-architected designs for sequential equivalence checking |
— |
2013-05-14 |
| 8429580 |
Method for preparing for and formally verifying a modified integrated circuit design |
Raymond Cheung Yeung, Irfan Waheed |
2013-04-23 |
| 8310268 |
Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design |
— |
2012-11-13 |
| 7956636 |
Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design |
— |
2011-06-07 |
| 6106567 |
Circuit design verification tool and method therefor using maxwell's equations |
Warren D. Grobman |
2000-08-22 |
| 5966306 |
Method for verifying protocol conformance of an electrical interface |
Harold M. Martin, Anhtu Nguyen |
1999-10-12 |