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Home › Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

US Patent 8399336 · Granted Mar 19, 2013

Estimated economic value: $8,741,000 ⓘ

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