Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing transistor junction capacitance by recessing drain and source regions

Reducing transistor junction capacitance by recessing drain and source regions

US Patent 7754556 · Granted Jul 13, 2010

Estimated economic value: $9,965,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Front-end-of-line device structure and method of forming such a front-end-of-lin2019
Method of forming a semiconductor structure including silicided and non-silicide2017
Methods for fabricating integrated circuits with robust gate electrode structure2015
Multi-step deposition of a spacer material for reducing void formation in a diel2015
High-K metal gate electrode structures formed by cap layer removal without sacri2015
Strain enhancement in transistors comprising an embedded strain-inducing semicon2015
Methods of reducing material loss in isolation structures by introducing inert a2014
Spacer for a gate electrode having tensile stress and a method of forming the sa2014
Three-dimensional semiconductor device comprising an inter-die connection on the2014
Complementary transistors comprising high-k metal gate electrode structures and 2014
NiSi rework procedure to remove platinum residuals2014
Strain enhancement in transistors comprising an embedded strain-inducing semicon2014