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Home › Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays

Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays

US Patent 7718448 · Granted May 18, 2010

Estimated economic value: $3,156,000 ⓘ

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