Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

US Patent 7220635 · Granted May 22, 2007

Estimated economic value: $18,006,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nanowire transistor fabrication with hardmask layers2025
Staggered vertically spaced integrated circuit line metallization with different2025
Non-contact optical measurement devices and exchangeable optical probes2025
Capacitor with dual dielectric layers2025
Subtractively patterned interconnect structures for integrated circuits2025
Capacitor with an electrically conductive layer coupled with a metal layer of th2025
Gate-all-around integrated circuit structures having germanium-diffused nanoribb2025
Compositional engineering of Schottky diode2025
Transistor gate trench engineering to decrease capacitance and resistance2025
Capacitor connections in dielectric layers2025
Formation of gate spacers for strained PMOS gate-all-around transistor structure2025
Integrated circuit interconnect structures with graphene cap2025