Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

US Patent 7217322 · Granted May 15, 2007

Estimated economic value: $13,934,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Device design for short-circuit protection of transistors2025
Semiconductor devices for high frequency applications2025
Power semiconductor devices with improved overcoat adhesion and/or protection2025
Mixed pitch track pattern2024
Methods of forming semiconductor power devices having graded lateral doping2023
Device design for short-circuitry protection circuitry within transistors2023
Semiconductor power devices having graded lateral doping in the source region2022
Fin-based devices based on the thermoelectric effect2021
Integrated circuit with resurf region biasing under buried insulator layers2021
Transistor having double isolation with one floating isolation2021
Method for producing a ceramic component composed of a plurality of joined prefo2020
FDSOI channel control by implanted high-k buried oxide2020