Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test circuit for delay lock loops

Test circuit for delay lock loops

US Patent 7061224 · Granted Jun 13, 2006

Estimated economic value: $12,187,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Alternating current coupled electronic component test system and method2017
Alternating current coupled electronic component test system and method2016
Even and odd frame combination data path architecture2012
Nibble de-skew method, apparatus, and system2011
Clock synchronization scheme for deskewing operations in a data interface2010
Method and apparatus for memory redundancy in a microprocessor2010
Clock deskewing method, apparatus, and system2010
Optimizing clock crossing and data path latency2009
Clocking architecture using a bidirectional clock port2009
Receive clock deskewing method, apparatus, and system2008
Nibble de-skew method, apparatus, and system2008
Modular memory controller clocking architecture2008