Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual damascene with a sacrificial via fill

Dual damascene with a sacrificial via fill

US Patent 5705430 · Granted Jan 6, 1998

Estimated economic value: $40,740,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs2019
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2019
Simplified gate to source/drain region connections2019
Method, apparatus, and system for using a cover mask for enabling metal line jum2018
Method, apparatus, and system for using a cover mask for enabling metal line jum2018
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2018
Pass-through contact using silicide2017
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs2017
CMOS circuit having a tensile stress layer overlying an NMOS transistor and over2016
Damascene metal-insulator-metal (MIM) device with improved scaleability2016
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs2015
SRAM cell with individual electrical device threshold control2015