Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

US Patent 10262905 · Granted Apr 16, 2019

Estimated economic value: $3,839,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Liner-less via contact2025
Semiconductor device having hybrid middle of line contacts2025
Vertically stacked FET with strained channel2025
Nanowire source/drain formation for nanosheet device2025
SRAM with staggered stacked FET2025
Strain generation and anchoring in gate-all-around field effect transistors2025
Buried power rail with robust connection to a wrap around contact2025
Semiconductor structure with wrapped-around backside contact2025
Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transist2025
Two-dimensional vertical fins2025
Gain cell memory based physically unclonable function2025
Method of making a semiconductor device using a dummy gate2025