Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Scan synchronous-write-through testing architectures for a memory device

Scan synchronous-write-through testing architectures for a memory device

US Patent 11734142 · Granted Aug 22, 2023

Estimated economic value: $8,181,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory device, method, layout, and system2025
Memory device with global and local latches2025
Semiconductor processing tool and methods of operation2025
Electronic device and display apparatus2025
Memory circuit and method of operating same2025
Memory device2025
Scan synchronous-write-through testing architectures for a memory device2025
Scan synchronous-write-through testing architectures for a memory device2025
Scan synchronous-write-through testing architectures for a memory device2025
Scan synchronous-write-through testing architectures for a memory device2025
Scan synchronous-write-through testing architectures for a memory device2025
Scan synchronous-write-through testing architectures for a memory device2025