{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Aspect ratio trapping (ART) for fabricating vertical semiconductor devices", "item": "https://www.patentleaderboard.com/patent/10096709"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

US Patent 10096709 · Granted Oct 9, 2018

Estimated economic value: $20,353,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nanowire transistor fabrication with hardmask layers2025
Nanowire transistor fabrication with hardmask layers2025
Staggered vertically spaced integrated circuit line metallization with different2025
Capacitor with dual dielectric layers2025
Dielectric sidewall features for tuning thin film transistor (TFT) parasitics2025
Subtractively patterned interconnect structures for integrated circuits2025
Punch-through interconnect feature to couple upper electrodes of capacitors of m2025
Gate-to-gate isolation for stacked transistor architecture via non-selective die2025
Trench-based quantum dot devices with conductive liners2025
Integrating embedded memory with logic interconnects2025
Method of forming capacitors through wafer bonding2025
Plug and recess process for dual metal gate on stacked nanoribbon devices2025