Issued Patents All Time
Showing 51–75 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8140945 | Hard component failure detection and correction | — | 2012-03-20 |
| 8117393 | Selectively performing lookups for cache lines | Haakan E. Zeffer | 2012-02-14 |
| 8103834 | Coherence protocol with dynamic privatization | Haakan E. Zeffer | 2012-01-24 |
| 8024526 | Multi-node system with global access states | Anders Landin, Erik E. Hagersten | 2011-09-20 |
| 8010749 | Multi-node computer system with proxy transaction to read data from a non-owning memory device | Anders Landin, Erik E. Hagersten | 2011-08-30 |
| 7979640 | Cache line duplication in response to a way prediction conflict | Shailender Chaudhry, Martin Karlsson | 2011-07-12 |
| 7962733 | Branch prediction mechanisms using multiple hash functions | Stevan Vlaovic | 2011-06-14 |
| 7949831 | Maintaining cache coherence using load-mark metadata to deny invalidation of load-marked cache lines | Shailender Chaudhry | 2011-05-24 |
| 7917698 | Method and apparatus for tracking load-marks and store-marks on cache lines | Shailender Chaudhry | 2011-03-29 |
| 7849290 | Store queue architecture for a processor that supports speculative execution | Shailender Chaudhry | 2010-12-07 |
| 7814278 | Multi-node system with response information in memory | — | 2010-10-12 |
| 7797491 | Facilitating load reordering through cacheline marking | Shailender Chaudhry | 2010-09-14 |
| 7779393 | System and method for efficient verification of memory consistency model compliance | Chaiyasit Manovit, Sudheendra Hangal | 2010-08-17 |
| 7774552 | Preventing store starvation in a system that supports marked coherence | Shailender Chaudhry | 2010-08-10 |
| 7757044 | Facilitating store reordering through cacheline marking | Shailender Chaudhry | 2010-07-13 |
| 7739456 | Method and apparatus for supporting very large transactions | Shailender Chaudhry | 2010-06-15 |
| 7730265 | Starvation-avoiding unbounded transactional memory | Shailender Chaudhry | 2010-06-01 |
| 7721042 | Content-addressable memory that supports a priority ordering between banks of differing sizes | — | 2010-05-18 |
| 7707554 | Associating data source information with runtime events | Nicolai Kosche, Mario I. Wolczko, John P. Petry, Adam R. Talcott | 2010-04-27 |
| 7698504 | Cache line marking with shared timestamps | Shailender Chaudhry | 2010-04-13 |
| 7680989 | Instruction set architecture employing conditional multistore synchronization | Mark S. Moir, Paul N. Loewenstein | 2010-03-16 |
| 7676729 | Data corruption avoidance in DRAM chip sparing | Charles Cheng, Michael Parkin | 2010-03-09 |
| 7676636 | Method and apparatus for implementing virtual transactional memory using cache line marking | Shailender Chaudhry, Anders Landin | 2010-03-09 |
| 7607069 | Computer system including network slices that map to field replaceable units | Drew G. Doblar | 2009-10-20 |
| 7606994 | Cache memory system including a partially hashed index | — | 2009-10-20 |