Issued Patents All Time
Showing 26–50 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8850120 | Store queue with store-merging and forward-progress guarantees | Haakan E. Zeffer | 2014-09-30 |
| 8756374 | Store queue supporting ordered and unordered stores | Haakan E. Zeffer | 2014-06-17 |
| 8732407 | Deadlock avoidance during store-mark acquisition | Haakan E. Zeffer, Shailender Chaudhry | 2014-05-20 |
| 8719675 | Orthogonal coding for data storage, access, and maintenance | — | 2014-05-06 |
| 8713258 | Estimating stack distances | — | 2014-04-29 |
| 8683294 | Efficient encoding of homed data | — | 2014-03-25 |
| 8645632 | Speculative writestream transaction | Haakan E. Zeffer, Anders Landin | 2014-02-04 |
| 8640000 | Nested coding techniques for data storage | — | 2014-01-28 |
| 8627044 | Issuing instructions with unresolved data dependencies | Shailender Chaudhry, Richard Van, Debasish Chandra | 2014-01-07 |
| 8621317 | Modified orthogonal coding techniques for storing data | — | 2013-12-31 |
| 8621156 | Labeled cache system | — | 2013-12-31 |
| 8621290 | Memory system that supports probalistic component-failure correction with partial-component sparing | Bharat Daga | 2013-12-31 |
| 8615698 | Skewed orthogonal coding techniques | — | 2013-12-24 |
| 8606997 | Cache hierarchy with bounds on levels accessed | Haakan E. Zeffer, Anders Landin | 2013-12-10 |
| 8601339 | Layered coding techniques for data storage | — | 2013-12-03 |
| 8516199 | Bandwidth-efficient directory-based coherence protocol | Haakan E. Zeffer, Brian J. McGee, Bharat Daga | 2013-08-20 |
| 8484438 | Hierarchical bloom filters for facilitating concurrency control | — | 2013-07-09 |
| 8484536 | Techniques for data storage, access, and maintenance | — | 2013-07-09 |
| 8464261 | System and method for executing a transaction using parallel co-transactions | Mark S. Moir, Daniel S. Nussbaum | 2013-06-11 |
| 8341357 | Pre-fetching for a sibling cache | Martin Karlsson, Shailender Chaudhry | 2012-12-25 |
| 8335961 | Facilitating probabilistic error detection and correction after a memory component failure | — | 2012-12-18 |
| 8335976 | Memory system that provides guaranteed component-failure correction with double-error correction | Bharat Daga | 2012-12-18 |
| 8296524 | Supporting efficient spin-locks and other types of synchronization in a cache-coherent multiprocessor system | Haakan E. Zeffer | 2012-10-23 |
| 8271735 | Cache-coherency protocol with held state | — | 2012-09-18 |
| 8255741 | Facilitating error detection and correction after a memory component failure | Bharat Daga | 2012-08-28 |