Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8645632 | Speculative writestream transaction | Robert E. Cypher, Haakan E. Zeffer | 2014-02-04 |
| 8606997 | Cache hierarchy with bounds on levels accessed | Robert E. Cypher, Haakan E. Zeffer | 2013-12-10 |
| 8102663 | Proximity communication package for processor, cache and memory | John E. Cunningham, Ashok V. Krishnamoorthy | 2012-01-24 |
| 8024526 | Multi-node system with global access states | Robert E. Cypher, Erik E. Hagersten | 2011-09-20 |
| 8010749 | Multi-node computer system with proxy transaction to read data from a non-owning memory device | Robert E. Cypher, Erik E. Hagersten | 2011-08-30 |
| 7945738 | Multi-node computer system employing a reporting mechanism for multi-node transactions | Erik E. Hagersten | 2011-05-17 |
| 7765381 | Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes | Erik E. Hagersten | 2010-07-27 |
| 7676636 | Method and apparatus for implementing virtual transactional memory using cache line marking | Robert E. Cypher, Shailender Chaudhry | 2010-03-09 |
| 7606978 | Multi-node computer system implementing global access state dependent transactions | Robert E. Cypher, Erik E. Hagersten | 2009-10-20 |
| 7529893 | Multi-node system with split ownership and access right coherence mechanism | Robert E. Cypher, Erik E. Hagersten | 2009-05-05 |
| 7509460 | DRAM remote access cache in local memory in a distributed shared memory system | Hakan Zeffer, Erik E. Hagersten | 2009-03-24 |
| 7480770 | Semi-blocking deterministic directory coherence | Hakan Zeffer | 2009-01-20 |
| 7412567 | Value-based memory coherence support | Hakan Zeffer, Erik E. Hagersten, Shailender Chaudhry, Paul N. Loewenstein, Robert E. Cypher +1 more | 2008-08-12 |
| 7376793 | Cache coherence protocol with speculative writestream | Robert E. Cypher | 2008-05-20 |
| 7363462 | Performing virtual to global address translation in processing subsystem | Erik E. Hagersten | 2008-04-22 |
| 7360056 | Multi-node system in which global address generated by processing subsystem includes global to local translation information | Robert E. Cypher, Erik E. Hagersten | 2008-04-15 |
| 7360029 | Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node | Robert E. Cypher | 2008-04-15 |
| 7120756 | Computer system including a promise array | Robert E. Cypher, Erik E. Hagersten | 2006-10-10 |
| 7055016 | Computer system including a memory controller configured to perform pre-fetch operations | Andrew Everett Phelps, Jurgen Schulz | 2006-05-30 |
| 6973547 | Coherence message prediction mechanism and multiprocessing computer system employing the same | Jim K. Nilsson, Per Stenström | 2005-12-06 |