Issued Patents All Time
Showing 176–200 of 237 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6438677 | Dynamic handling of object versions to support space and time dimensional program execution | Shailender Chaudhry | 2002-08-20 |
| 6430649 | Method and apparatus for enforcing memory reference dependencies through a load store unit | Shailender Chaudhry, James M. O'Connor | 2002-08-06 |
| 6415356 | Method and apparatus for using an assist processor to pre-fetch data values for a primary processor | Shailender Chaudhry | 2002-07-02 |
| 6413229 | Force-feedback interface device for the hand | James F. Kramer, Mark H. Yim, Daniel H. Gomez | 2002-07-02 |
| 6408383 | Array access boundary check by executing BNDCHK instruction with comparison specifiers | James M. O'Connor | 2002-06-18 |
| 6405300 | Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor | William N. Joy | 2002-06-11 |
| 6401175 | Shared write buffer for use by multiple processor units | Andre Kowalczyk, Anup S. Tirumala | 2002-06-04 |
| 6378041 | Shared instruction cache for multiple processors | — | 2002-04-23 |
| 6374351 | Software branch prediction filtering for a microprocessor | — | 2002-04-16 |
| 6353881 | Supporting space-time dimensional program execution by selectively versioning memory updates | Shailender Chaudhry | 2002-03-05 |
| 6351808 | Vertically and horizontally threaded processor with multidimensional storage for storing thread data | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2002-02-26 |
| 6349381 | Pipelined instruction dispatch unit in a superscalar processor | — | 2002-02-19 |
| 6343348 | Apparatus and method for optimizing die utilization and speed performance by register file splitting | William N. Joy | 2002-01-29 |
| 6341348 | Software branch prediction filtering for a microprocessor | — | 2002-01-22 |
| 6341347 | Thread switch logic in a multiple-thread processor | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2002-01-22 |
| 6321325 | Dual in-line buffers for an instruction fetch unit | Graham Ricketson Murphy | 2001-11-20 |
| 6314509 | Efficient method for fetching instructions having a non-power of two size | Graham Ricketson Murphy | 2001-11-06 |
| 6282637 | Partially executing a pending atomic instruction to unlock resources when cancellation of the instruction occurs | Jeffrey Meng Wah Chan | 2001-08-28 |
| 6282617 | Multiple variable cache replacement policy | Anup S. Tirumala | 2001-08-28 |
| 6279100 | Local stall control method and structure in a microprocessor | Sharada Yeluri | 2001-08-21 |
| 6249861 | Instruction fetch unit aligner for a non-power of two size VLIW instruction | Graham Ricketson Murphy, Frank C. Chiu | 2001-06-19 |
| 6247027 | Facilitating garbage collection during object versioning for space and time dimensional computing | Shailender Chaudhry | 2001-06-12 |
| D443424 | Clothes hanger | Stanley Eiley | 2001-06-12 |
| 6237066 | Supporting multiple outstanding requests to multiple targets in a pipelined memory system | Bi-Yu Pan | 2001-05-22 |
| 6233667 | Method and apparatus for a high-performance embedded memory management unit | Nik Shaylor, Jeffrey Meng Wah Chan, Gary Oblock | 2001-05-15 |