Issued Patents All Time
Showing 151–175 of 237 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6694347 | Switching method in a multi-threaded processor | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2004-02-17 |
| D486553 | Watering can | — | 2004-02-10 |
| 6684398 | Monitor entry and exit for a speculative thread during space and time dimensional execution | Shailender Chaudhry | 2004-01-27 |
| 6684297 | Reverse directory for facilitating accesses involving a lower-level cache | Shailender Chaudhry | 2004-01-27 |
| 6681318 | Method and apparatus for using an assist processor to prefetch instructions for a primary processor | Shailender Chaudhry | 2004-01-20 |
| 6671796 | Converting an arbitrary fixed point value to a floating point value | Subramania Sudharsanan, Jeffrey Meng Wah Chan, Michael F. Deering, Scott R. Nelson | 2003-12-30 |
| 6658451 | Parallel join operation to support space and time dimensional program execution | Shailender Chaudhry | 2003-12-02 |
| 6628277 | Decompression of three-dimensional graphics data using mesh buffer references to reduce redundancy of processing | Michael F. Deering, Jeffrey Meng Wah Chan | 2003-09-30 |
| 6625634 | Efficient implementation of multiprecision arithmetic | Chandramouli Banerjee | 2003-09-23 |
| 6622219 | Shared write buffer for use by multiple processor units | Andre Kowalczyk, Anup S. Tirumala | 2003-09-16 |
| 6615338 | Clustered architecture in a VLIW processor | William N. Joy | 2003-09-02 |
| 6571319 | Methods and apparatus for combining a plurality of memory access transactions | Shrinath A. Keskar | 2003-05-27 |
| 6559842 | Compressing and decompressing graphics data using gosub-type instructions and direct and indirect attribute settings | Michael F. Deering, Jeffrey Meng Wah Chan | 2003-05-06 |
| 6542988 | Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file | Jeffrey Meng Wah Chan, Subramania Sudharsanan, Sharada Yeluri, Biyu Pan | 2003-04-01 |
| 6542990 | Array access boundary check by executing BNDCHK instruction with comparison specifiers | James M. O'Connor | 2003-04-01 |
| 6542991 | Multiple-thread processor with single-thread interface shared among threads | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2003-04-01 |
| 6532531 | Method frame storage using multiple memory circuits | James M. O'Connor | 2003-03-11 |
| 6529982 | Locking of computer resources | William N. Joy, James M. O'Connor | 2003-03-04 |
| 6523091 | Multiple variable cache replacement policy | Anup S. Tirumala | 2003-02-18 |
| 6523090 | Shared instruction cache for multiple processors | — | 2003-02-18 |
| 6507862 | Switching method in a multi-threaded processor | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2003-01-14 |
| 6499097 | Instruction fetch unit aligner for a non-power of two size VLIW instruction | Graham Ricketson Murphy, Frank C. Chiu | 2002-12-24 |
| 6463526 | Supporting multi-dimensional space-time computing through object versioning | Shailender Chaudhry | 2002-10-08 |
| 6460067 | Using time stamps to improve efficiency in marking fields within objects | Shailender Chaudhry | 2002-10-01 |
| 6453463 | Method and apparatus for providing finer marking granularity for fields within objects | Shailender Chaudhry | 2002-09-17 |