Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7587582 | Method and apparatus for parallel arithmetic operations | Subramania Sudharsanan, Michael F. Deering, Marc Tremblay, Scott R. Nelson | 2009-09-08 |
| 7427991 | System and process for digital generation, placement, animation and display of feathers and other surface-attached geometry for computer generated imagery | Armin Walter Bruderlin, Robert B. Engle, Gokhan Kisacikoglu, Brian Steiner, David S. Tanner | 2008-09-23 |
| 7071935 | Graphics system with just-in-time decompression of compressed graphics data | Michael F. Deering, Marc Tremblay | 2006-07-04 |
| 7042466 | Efficient clip-testing in graphics acceleration | Michael F. Deering | 2006-05-09 |
| 6757820 | Decompression bit processing with a general purpose alignment tool | Subramania Sudharsanan, Marc Tremblay | 2004-06-29 |
| 6671796 | Converting an arbitrary fixed point value to a floating point value | Subramania Sudharsanan, Michael F. Deering, Marc Tremblay, Scott R. Nelson | 2003-12-30 |
| 6628277 | Decompression of three-dimensional graphics data using mesh buffer references to reduce redundancy of processing | Michael F. Deering, Marc Tremblay | 2003-09-30 |
| 6559842 | Compressing and decompressing graphics data using gosub-type instructions and direct and indirect attribute settings | Michael F. Deering, Marc Tremblay | 2003-05-06 |
| 6542988 | Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file | Marc Tremblay, Subramania Sudharsanan, Sharada Yeluri, Biyu Pan | 2003-04-01 |
| 6407740 | Addressable output buffer architecture | — | 2002-06-18 |
| 6282637 | Partially executing a pending atomic instruction to unlock resources when cancellation of the instruction occurs | Marc Tremblay | 2001-08-28 |
| 6233667 | Method and apparatus for a high-performance embedded memory management unit | Nik Shaylor, Gary Oblock, Marc Tremblay | 2001-05-15 |
| 6163837 | Writing of instruction results produced by instruction execution circuits to result destinations | Subramania Sudharsanan, Marc Tremblay | 2000-12-19 |
| 6028607 | Method of producing a sequence of triangles from a vertex raster with and without half resolution edges while decompressing a compressed geometry stream | — | 2000-02-22 |