Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8589854 | Application driven power gating | Pius Ng, Satish Padmanabhan, Anand Pandurangan, Ananth Durbha, Suresh Kadiyala | 2013-11-19 |
| 8572544 | Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization | Ananth Durbha, Pius Ng, Suresh Kadiyala, Satish Padmanabhan | 2013-10-29 |
| 8561005 | Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design | Ananth Durbha, Pius Ng, Suresh Kadiyala, Satish Padmanabhan | 2013-10-15 |
| 8185862 | Architectural level power-aware optimization and risk mitigation | Ananth Durbha, Pius Ng, Suresh Kadiyala, Satish Padmanabhan | 2012-05-22 |
| 6233667 | Method and apparatus for a high-performance embedded memory management unit | Nik Shaylor, Jeffrey Meng Wah Chan, Marc Tremblay | 2001-05-15 |
| 5943691 | Determination of array padding using collision vectors | David R. Wallace | 1999-08-24 |