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Ananth Durbha, Pius Ng, Suresh Kadiyala, Satish Padmanabhan |
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| 8561005 |
Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design |
Ananth Durbha, Pius Ng, Suresh Kadiyala, Satish Padmanabhan |
2013-10-15 |
| 8185862 |
Architectural level power-aware optimization and risk mitigation |
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Method and apparatus for a high-performance embedded memory management unit |
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Determination of array padding using collision vectors |
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