Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11803508 | Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2023-10-31 |
| 11449459 | Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2022-09-20 |
| 11086574 | Machine perception and dense algorithm integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2021-08-10 |
| 10997115 | Systems and methods for implementing a machine perception and dense algorithm integrated circuit and enabling a flowing propagation of data within the integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2021-05-04 |
| 10761848 | Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Daniel Firu, Veerbhan Kheterpal | 2020-09-01 |
| 10642541 | Machine perception and dense algorithm integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2020-05-05 |
| 10474398 | Machine perception and dense algorithm integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2019-11-12 |
| 10365860 | Machine perception and dense algorithm integrated circuit | Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Robert Daniel Firu, Veerbhan Kheterpal | 2019-07-30 |
| 8589854 | Application driven power gating | Pius Ng, Satish Padmanabhan, Anand Pandurangan, Suresh Kadiyala, Gary Oblock | 2013-11-19 |
| 8572544 | Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization | Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan | 2013-10-29 |
| 8561005 | Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design | Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan | 2013-10-15 |
| 8516416 | Integrated data model based framework for driving design convergence from architecture optimization to physical design closure | Satish Padmanabhan, Plus Ng | 2013-08-20 |
| 8423929 | Intelligent architecture creator | Anand Pandurangan, Pius Ng, Siva Selvaraj, Sanjay Banerjee, Suresh Kadiyala +1 more | 2013-04-16 |
| 8370784 | Automatic optimal integrated circuit generator from algorithms and specification | Satish Padmanabhan, Plus Ng, Anand Pandurangan, Suresh Kadiyala, Tak Shigihara | 2013-02-05 |
| 8276107 | Integrated data model based framework for driving design convergence from architecture optimization to physical design closure | Satish Padmanabhan, Pius Ng | 2012-09-25 |
| 8225247 | Automatic optimal integrated circuit generator from algorithms and specification | Satish Padmanabhan, Pius Ng, Anand Pandurangan, Suresh Kadiyala, Tak Shigihara | 2012-07-17 |
| 8185862 | Architectural level power-aware optimization and risk mitigation | Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan | 2012-05-22 |