Issued Patents All Time
Showing 101–125 of 237 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7269717 | Method for reducing lock manipulation overhead during access to critical code sections | Shailender Chaudhry, Quinn A. Jacobson | 2007-09-11 |
| 7269694 | Selectively monitoring loads to support transactional program execution | Quinn A. Jacobson, Shailender Chaudhry | 2007-09-11 |
| 7269693 | Selectively monitoring stores to support transactional program execution | Quinn A. Jacobson, Shailender Chaudhry | 2007-09-11 |
| 7263603 | Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor | Shailender Chaudhry, Paul Caprioli | 2007-08-28 |
| 7257700 | Avoiding register RAW hazards when returning from speculative execution | Shailender Chaudhry, Paul Caprioli, Sherman H. Yip | 2007-08-14 |
| 7257699 | Selective execution of deferred instructions in a processor that supports speculative execution | Shailender Chaudhry, Paul Caprioli | 2007-08-14 |
| 7216219 | Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor | Shailender Chaudhry, Paul Caprioli | 2007-05-08 |
| 7216202 | Method and apparatus for supporting one or more servers on a single semiconductor chip | Shailender Chaudhry, Quinn A. Jacobson | 2007-05-08 |
| 7206903 | Method and apparatus for releasing memory locations during transactional execution | Mark S. Moir, Maurice P. Herlihy, Quinn A. Jacobson, Shailender Chaudhry | 2007-04-17 |
| 7185185 | Multiple-thread processor with in-pipeline, thread selectable storage | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2007-02-27 |
| 7168076 | Facilitating efficient join operations between a head thread and a speculative thread | Shailender Chaudhry | 2007-01-23 |
| 7152232 | Hardware message buffer for supporting inter-processor communication | Shailender Chaudhry | 2006-12-19 |
| 7127643 | Method and apparatus for fixing bit errors encountered during cache references without blocking | Shailender Chaudhry | 2006-10-24 |
| 7124331 | Method and apparatus for providing fault-tolerance for temporary results within a CPU | Shailender Chaudhry, Quinn A. Jacobson | 2006-10-17 |
| 7117342 | Implicitly derived register specifiers in a processor | William N. Joy | 2006-10-03 |
| 7114060 | Selectively deferring instructions issued in program order utilizing a checkpoint and multiple deferral scheme | Shailender Chaudhry | 2006-09-26 |
| 7114056 | Local and global register partitioning in a VLIW processor | William N. Joy | 2006-09-26 |
| 7089374 | Selectively unmarking load-marked cache lines during transactional program execution | Quinn A. Jacobson, Shailender Chaudhry, Mark S. Moir, Maurice P. Herlihy | 2006-08-08 |
| 7071935 | Graphics system with just-in-time decompression of compressed graphics data | Michael F. Deering, Jeffrey Meng Wah Chan | 2006-07-04 |
| 7058877 | Method and apparatus for providing error correction within a register file of a CPU | Shailender Chaudhry, Quinn A. Jacobson | 2006-06-06 |
| 7051192 | Facilitating value prediction to support speculative program execution | Shailender Chaudhry | 2006-05-23 |
| 7050955 | System, method and data structure for simulated interaction with graphical objects | Ron Carmel, Hugo J. C. DesRosiers, Daniel H. Gomez, James F. Kramer, Jerry Tian +1 more | 2006-05-23 |
| 7013454 | Thread suspension system and method using trapping instructions | William R. Bush, Mario I. Wolczko | 2006-03-14 |
| 7010674 | Efficient handling of a large register file for context switching and function calls and returns | William N. Joy | 2006-03-07 |
| 6988121 | Efficient implementation of multiprecision arithmetic | Chandramouli Banerjee | 2006-01-17 |