Issued Patents All Time
Showing 76–100 of 237 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7587581 | Multiple-thread processor with in-pipeline, thread selectable storage | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2009-09-08 |
| 7584346 | Method and apparatus for supporting different modes of multi-threaded speculative execution | Shailender Chaudhry, Paul Caprioli | 2009-09-01 |
| 7574588 | Time-multiplexed speculative multi-threading to support single-threaded applications | Shailender Chaudhry | 2009-08-11 |
| 7571304 | Generation of multiple checkpoints in a processor that supports speculative execution | Shailender Chaudhry, Paul Caprioli | 2009-08-04 |
| 7565511 | Working register file entries with instruction based lifetime | Shailender Chaudhry, Quinn A. Jacobson | 2009-07-21 |
| 7523266 | Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level | Shailender Chaudhry | 2009-04-21 |
| 7519775 | Enforcing memory-reference ordering requirements at the L2 cache level | Shailender Chaudhry | 2009-04-14 |
| 7509481 | Patchable and/or programmable pre-decode | Shailender Chaudhry, Paul Caprioli, Quinn A. Jacobson | 2009-03-24 |
| 7500086 | Start transactional execution (STE) instruction to support transactional program execution | Shailender Chaudhry, Quinn A. Jacobson | 2009-03-03 |
| 7490228 | Processor with register dirty bit tracking for efficient context switch | William N. Joy | 2009-02-10 |
| 7490229 | Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution | Shailender Chaudhry, Quinn A. Jacobson | 2009-02-10 |
| 7484080 | Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer | Shailender Chaudhry, Paul Caprioli | 2009-01-27 |
| 7469334 | Method and apparatus for facilitating a fast restart after speculative execution | Shailender Chaudhry, Quinn A. Jacobson | 2008-12-23 |
| 7437534 | Local and global register partitioning technique | William N. Joy | 2008-10-14 |
| 7430653 | Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking | — | 2008-09-30 |
| 7418577 | Fail instruction to support transactional program execution | Shailender Chaudhry, Quinn A. Jacobson | 2008-08-26 |
| 7398355 | Avoiding locks by transactionally executing critical sections | Mark S. Moir, Shailender Chaudhry | 2008-07-08 |
| 7389383 | Selectively unmarking load-marked cache lines during transactional program execution | Quinn A. Jacobson, Shailender Chaudhry, Mark S. Moir, Maurice P. Herlihy | 2008-06-17 |
| 7366880 | Facilitating value prediction to support speculative program execution | Shailender Chaudhry | 2008-04-29 |
| 7360028 | Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol | — | 2008-04-15 |
| 7353363 | Patchable and/or programmable decode using predecode selection | Shailender Chaudhry, Paul Caprioli, Quinn A. Jacobson | 2008-04-01 |
| 7316021 | Switching method in a multi-threaded processor | William N. Joy, Gary R. Lauterbach, Joseph I. Chamdani | 2008-01-01 |
| 7293160 | Mechanism for eliminating the restart penalty when reissuing deferred instructions | Shailender Chaudhry, Paul Caprioli | 2007-11-06 |
| 7293161 | Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode | Shailender Chaudhry, Paul Caprioli | 2007-11-06 |
| 7277989 | Selectively performing fetches for store operations during speculative execution | Shailender Chaudhry, Paul Caprioli | 2007-10-02 |