Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277043 | Test data authentication and processing using scalable data structures | Smbat Tonoyan | 2025-04-15 |
| 11940493 | Flexible one-hot decoding logic for clock controls | Vinod Pagalone, Munish Aggarwal, Doochul Shin | 2024-03-26 |
| 11526644 | Controlling test networks of chips using integrated processors | Kaushik Narayanun, Shantanu Sarangi, Jae Wu | 2022-12-13 |
| 10473720 | Dynamic independent test partition clock | Pavan Kumar Datla Jagannadha, Dheepakkumaran Jayaraman, Anubhav Sinha, Karthikeyan Natarajan, Shantanu Sarangi +2 more | 2019-11-12 |
| 10451676 | Method and system for dynamic standard test access (DSTA) for a logic block reuse | Milind Sonawane, Amit Sanghani, Shantanu Sarangi, Jonathon E. Colburn, Bala Tarun Nelapatla +3 more | 2019-10-22 |
| 10444280 | Independent test partition clock coordination across multiple test partitions | Dheepakkumaran Jayaraman, Karthikeyan Natarajan, Shantanu Sarangi, Amit Sanghani, Milind Sonawane +4 more | 2019-10-15 |
| 10281524 | Test partition external input/output interface control for test partitions in a semiconductor | Sailendra Chadalavda, Shantanu Sarangi, Milind Sonawane, Amit Sanghani, Jonathon E. Colburn +2 more | 2019-05-07 |