Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10282297 | Read-with overridable-invalidate transaction | Phanindra Kumar Mannava, Jamshed Jalal, Mark David Werkheiser | 2019-05-07 |
| 10223002 | Compare-and-swap transaction | Phanindra Kumar Mannava, Klas Magnus Bruce, Geoffray Matthieu Lacourba | 2019-03-05 |
| 10185663 | Cache bypass | Jamshed Jalal, Michael Filippo, Phanindra Kumar Mannava | 2019-01-22 |
| 9830294 | Data processing system and method for handling multiple transactions using a multi-transaction request | Daren Croxford, Jason Parker | 2017-11-28 |
| 9569365 | Store-exclusive instruction conflict resolution | Stuart David Biles, Richard Roy Grisenthwaite | 2017-02-14 |
| 9477623 | Barrier transactions in interconnects | Peter Andrew Riocreux, Christopher William Laycock, Richard Roy Grisenthwaite | 2016-10-25 |
| 8856408 | Reduced latency barrier transaction requests in interconnects | Peter Andrew Riocreux, Christopher William Laycock, Richard Roy Grisenthwaite | 2014-10-07 |
| 8732400 | Data store maintenance requests in interconnects | Peter Andrew Riocreux, Christopher William Laycock, Richard Roy Grisenthwaite | 2014-05-20 |
| 8607006 | Barrier transactions in interconnects | Peter Andrew Riocreux, Christopher William Laycock, Richard Roy Grisenthwaite | 2013-12-10 |
| 8589631 | Coherency control with writeback ordering | Christopher William Laycock, Antony John Harris, Stuart David Biles | 2013-11-19 |
| 8463958 | Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices | Phanindra Kumar Mannava, Jamshed Jalal, Ramamoorthy Guru Prasadh, Michael Filippo, Timothy Charles Mace | 2013-06-11 |
| 8463966 | Synchronising activities of various components in a distributed system | Peter Andrew Riocreux, Christopher William Laycock, Richard Roy Grisenthwaite | 2013-06-11 |
| 8375170 | Apparatus and method for handling data in a cache | Christopher William Laycock, Antony John Harris, Andrew Christopher Rose, Richard Roy Grisenthwaite | 2013-02-12 |
| 8190801 | Interconnect logic for a data processing apparatus | Antony John Harris | 2012-05-29 |
| 8045573 | Bit ordering for packetised serial data transmission on an integrated circuit | Antony John Harris | 2011-10-25 |
| 7925840 | Data processing apparatus and method for managing snoop operations | Antony John Harris, Christopher William Laycock | 2011-04-12 |
| 7757027 | Control of master/slave communication within an integrated circuit | Christopher William Laycock, Antony John Harris, Richard Roy Grisenthwaite, Stuart David Biles | 2010-07-13 |
| 7599998 | Message handling communication between a source processor core and destination processor cores | Mark James Galbraith, Harry Samuel Thomas Fearnhamm, Nicholas E. Smith | 2009-10-06 |
| 7353297 | Handling of write transactions in a data processing apparatus | Antony John Harris | 2008-04-01 |
| 7290075 | Performing arbitration in a data processing apparatus | Alistair Crone Bruce, Antony John Harris | 2007-10-30 |
| 7254658 | Write transaction interleaving | Antony John Harris | 2007-08-07 |
| 7219178 | Bus deadlock avoidance | Antony John Harris, Christopher Wrigley | 2007-05-15 |
| 7213092 | Write response signalling within a communication bus | Antony John Harris | 2007-05-01 |
| 7213095 | Bus transaction management within data processing systems | Peter Guy Middleton, David John Gwilt, Ian Victor Devereux, Antony John Harris, Richard Roy Grisenthwaite | 2007-05-01 |
| 7143221 | Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus | Alistair Crone Bruce, Antony John Harris | 2006-11-28 |