Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10062644 | Copper interconnect for improving radio frequency (RF) silicon-on-insulator (SOI) switch field effect transistor (FET) stacks | David J. Howard | 2018-08-28 |
| 10044331 | High power RF switches using multiple optimized transistors | Roda Kanawati | 2018-08-07 |
| 9966301 | Reduced substrate effects in monolithically integrated RF circuits | David J. Howard, Michael J. DeBar | 2018-05-08 |
| 9941353 | Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology | Edward Preisler, Marco Racanelli | 2018-04-10 |
| 9917104 | Hybrid MOS-PCM CMOS SOI switch | Yakov Roizin, David J. Howard | 2018-03-13 |
| 9754814 | Integrated passive device having improved linearity and isolation | — | 2017-09-05 |
| 9634089 | Selective amorphization for signal isolation and linearity | Robert L. Zwingman | 2017-04-25 |
| 9620617 | Structure and method for reducing substrate parasitics in semiconductor on insulator technology | — | 2017-04-11 |
| 9608079 | Semiconductor device having reduced drain-to-source capacitance | Roda Kanawati | 2017-03-28 |
| 9577035 | Isolated through silicon vias in RF technologies | Edward Preisler, Hadi Jebory | 2017-02-21 |
| 9362160 | SOI structure and method for utilizing trenches for signal isolation and linearity | Robert L. Zwingman | 2016-06-07 |
| 9343353 | SOI structure for signal isolation and linearity | Robert L. Zwingman | 2016-05-17 |
| 9190994 | RF switch branch having improved linearity | — | 2015-11-17 |
| 9105681 | Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Volker Blaschke, Todd Thibeault, Chris Cureton, Arjun Kar-Roy, David J. Howard +1 more | 2015-08-11 |
| 8963247 | Selective amorphization for electrical signal isolation and linearity in SOI structures | Robert L. Zwingman | 2015-02-24 |
| 8956949 | Electrical signal isolation in semiconductor structures | Robert L. Zwingman | 2015-02-17 |
| 8816471 | Electrical signal isolation and linearity in SOI structures | Robert L. Zwingman | 2014-08-26 |
| 8598713 | Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Volker Blaschke, Todd Thibeault, Chris Cureton, Arjun Kar-Roy, David J. Howard +1 more | 2013-12-03 |
| 7863148 | Method for integrating SiGe NPN and vertical PNP devices | Kenneth M. Ring, Chun Hu, Amol Kalburge | 2011-01-04 |
| 7541231 | Integration of SiGe NPN and vertical PNP devices on a substrate | Kenneth M. Ring, Chun Hu, Amol Kalburge | 2009-06-02 |
| 6933202 | Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure | Kenneth M. Ring, Chun Hu, Amol Kalburge | 2005-08-23 |