Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7994611 | Bipolar transistor fabricated in a biCMOS process | Kevin Q. Yin, Kenneth M. Ring | 2011-08-09 |
| 7871851 | Method for integrating nanotube devices with CMOS for RF/analog SoC applications | — | 2011-01-18 |
| 7863148 | Method for integrating SiGe NPN and vertical PNP devices | Paul D. Hurwitz, Kenneth M. Ring, Chun Hu | 2011-01-04 |
| 7858454 | Self-aligned T-gate carbon nanotube field effect transistor devices and method for forming the same | — | 2010-12-28 |
| 7816906 | Method for determining anisotropy of 1-D conductor or semiconductor synthesis | Zhen Yu | 2010-10-19 |
| 7772673 | Deep trench isolation and method for forming same | Kevin Q. Yin, David J. Howard, Arjun Kar-Roy, Dieter Dornisch | 2010-08-10 |
| 7541231 | Integration of SiGe NPN and vertical PNP devices on a substrate | Paul D. Hurwitz, Kenneth M. Ring, Chun Hu | 2009-06-02 |
| 7291536 | Fabricating a self-aligned bipolar transistor having increased manufacturability | Kevin Q. Yin, Kenneth M. Ring | 2007-11-06 |
| 7282418 | Method for fabricating a self-aligned bipolar transistor without spacers | Kevin Q. Yin | 2007-10-16 |
| 7064415 | Self-aligned bipolar transistor having increased manufacturability | Kevin Q. Yin, Kenneth M. Ring | 2006-06-20 |
| 7041564 | Method for fabricating a self-aligned bipolar transistor | Marco Racanelli | 2006-05-09 |
| 7033898 | Method for fabricating a self-aligned bipolar transistor having recessed spacers | Kevin Q. Yin | 2006-04-25 |
| 7015115 | Method for forming deep trench isolation and related structure | Kevin Q. Yin | 2006-03-21 |
| 6995449 | Deep trench isolation region with reduced-size cavities in overlying field oxide | Kevin Q. Yin | 2006-02-07 |
| 6992338 | CMOS transistor spacers formed in a BiCMOS process | Kevin Q. Yin, Klaus Schuegraf | 2006-01-31 |
| 6979626 | Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure | Kevin Q. Yin, Kenneth M. Ring | 2005-12-27 |
| 6933202 | Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure | Paul D. Hurwitz, Kenneth M. Ring, Chun Hu | 2005-08-23 |
| 6894328 | Self-aligned bipolar transistor having recessed spacers and method for fabricating same | Kevin Q. Yin | 2005-05-17 |
| 6867440 | Self-aligned bipolar transistor without spacers and method for fabricating same | Kevin Q. Yin | 2005-03-15 |
| 6830967 | Method for forming CMOS transistor spacers in a BiCMOS process | Kevin Q. Yin, Klaus Schuegraf | 2004-12-14 |
| 6809353 | Method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure | Marco Racanelli | 2004-10-26 |
| 6797580 | Method for fabricating a bipolar transistor in a BiCMOS process and related structure | Kevin Q. Yin, Kenneth M. Ring | 2004-09-28 |
| 6784467 | Method for fabricating a self-aligned bipolar transistor and related structure | Marco Racanelli | 2004-08-31 |
| 6770541 | Method for hard mask removal for deep trench isolation and related structure | Kevin Q. Yin | 2004-08-03 |
| 6764913 | Method for controlling an emitter window opening in an HBT and related structure | Kevin Q. Yin, Klaus Schuegraf | 2004-07-20 |