Issued Patents All Time
Showing 1–25 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12347673 | Method for forming a semiconductor structure having a porous semiconductor layer in RF devices | Paul D. Hurwitz, Edward Preisler, David J. Howard | 2025-07-01 |
| 11195920 | Semiconductor structure having porous semiconductor segment for RF devices and bulk semiconductor region for non-RF devices | Paul D. Hurwitz, Edward Preisler, David J. Howard | 2021-12-07 |
| 11164740 | Semiconductor structure having porous semiconductor layer for RF devices | Paul D. Hurwitz, Edward Preisler, David J. Howard | 2021-11-02 |
| 10991631 | High performance SiGe heterojunction bipolar transistors built on thin-film silicon-on-insulator substrates for radio frequency applications | Edward Preisler, Paul D. Hurwitz, David J. Howard | 2021-04-27 |
| 10622262 | High performance SiGe heterojunction bipolar transistors built on thin film silicon-on-insulator substrates for radio frequency applications | Edward Preisler, Paul D. Hurwitz, David J. Howard | 2020-04-14 |
| 10177045 | Bulk CMOS RF switch with reduced parasitic capacitance | Edward Preisler, Paul D. Hurwitz | 2019-01-08 |
| 10177044 | Bulk CMOS RF switch with reduced parasitic capacitance | Edward Preisler, Paul D. Hurwitz | 2019-01-08 |
| 9941353 | Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology | Paul D. Hurwitz, Edward Preisler | 2018-04-10 |
| 9673081 | Isolated through silicon via and isolated deep silicon via having total or partial isolation | Hadi Jebory, David J. Howard, Edward Preisler | 2017-06-06 |
| 9412758 | Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication | Robert L. Zwingman | 2016-08-09 |
| 9136157 | Deep N wells in triple well structures | Arjun Kar-Roy, Jinshu Zhang | 2015-09-15 |
| 9105681 | Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Volker Blaschke, Todd Thibeault, Chris Cureton, Paul D. Hurwitz, Arjun Kar-Roy +1 more | 2015-08-11 |
| 8598713 | Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation | Volker Blaschke, Todd Thibeault, Chris Cureton, Paul D. Hurwitz, Arjun Kar-Roy +1 more | 2013-12-03 |
| 8212331 | Method for fabricating a backside through-wafer via in a processed wafer and related structure | Arjun Kar-Roy, David J. Howard | 2012-07-03 |
| 7897484 | Fabricating a top conductive layer in a semiconductor die | Arjun Kar-Roy, David J. Howard | 2011-03-01 |
| 7745886 | Semiconductor on insulator (SOI) switching circuit | Robert L. Zwingman | 2010-06-29 |
| 7704874 | Method for fabricating a frontside through-wafer via in a processed wafer and related structure | Arjun Kar-Roy, David J. Howard | 2010-04-27 |
| 7589009 | Method for fabricating a top conductive layer in a semiconductor die and related structure | Arjun Kar-Roy, David J. Howard | 2009-09-15 |
| 7235861 | NPN transistor having reduced extrinsic base resistance and improved manufacturability | David J. Howard, Greg D. U'Ren | 2007-06-26 |
| 7217613 | Low cost fabrication of high resistivity resistors | — | 2007-05-15 |
| 7154161 | Composite ground shield for passive components in a semiconductor die | Volker Blaschke | 2006-12-26 |
| 7078310 | Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies | Arjun Kar-Roy, Paul Kempf | 2006-07-18 |
| 7078786 | Composite series resistor having reduced temperature sensitivity in an IC chip | Chun Hu, Chih-Chieh SHEN | 2006-07-18 |
| 7064361 | NPN transistor having reduced extrinsic base resistance and improved manufacturability | David J. Howard, Greg D. U'Ren | 2006-06-20 |
| 7052966 | Deep N wells in triple well structures and method for fabricating same | Arjun Kar-Roy, Jinshu Zhang | 2006-05-30 |