Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6694488 | System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners | Ganesh Lakshminarayana, Kanishka Lahiri | 2004-02-17 |
| 6625781 | Multi-level power macromodeling | Wolfgang Roethig, Ganesh Lakshminarayana, Arun Balakrishnan | 2003-09-23 |
| 6324679 | Register transfer level power optimization with emphasis on glitch analysis and reduction | Sujit Dey | 2001-11-27 |
| 6308313 | Method for synthesis of common-case optimized circuits to improve performance and power dissipation | Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha | 2001-10-23 |
| 6275969 | Common case optimized circuit structure for high-performance and low-power VLSI designs | Ganesh Lakshminarayana | 2001-08-14 |
| 6195786 | Constrained register sharing technique for low power VLSI design | Sujit Dey, Ganesh Lakshminarayana, Niraj K. Jha | 2001-02-27 |
| 6163876 | Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow | Pranav Ashar, Subhrajit Bhattacharya, Akira MUKAIYAMA | 2000-12-19 |
| 6105139 | Controller-based power management for low-power sequential circuits | Sujit Dey, Niraj K. Jha | 2000-08-15 |
| 5831864 | Design tools for high-level synthesis of a low-power data path | Niraj K. Jha | 1998-11-03 |
| 5726996 | Process for dynamic composition and test cycles reduction | Srimat Chakradhar | 1998-03-10 |