Issued Patents All Time
Showing 201–225 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6838711 | Power MOS arrays with non-uniform polygate length | Philipp Lindorfer, Vludislav Vashchenko, Rob Drury | 2005-01-04 |
| 6822294 | High holding voltage LVTSCR | Vladislav Vashchenko, Ann Concannon | 2004-11-23 |
| 6806529 | Memory cell with a capacitive structure as a control gate and method of forming the memory cell | Yuri Mirgorodski, Andy Strachan | 2004-10-19 |
| 6798641 | Low cost, high density diffusion diode-capacitor | Philipp Lindorfer, Vladislav Vashchenko, Andrew Strachan | 2004-09-28 |
| 6797555 | Direct implantation of fluorine into the channel region of a PMOS device | Prasad Chaparala, Philipp Lindorfer, Vladislav Vashchenko | 2004-09-28 |
| 6784029 | Bi-directional ESD protection structure for BiCMOS technology | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2004-08-31 |
| 6777784 | Bipolar transistor-based electrostatic discharge (ESD) protection structure with a heat sink | Vladislav Vashchenko | 2004-08-17 |
| 6740956 | Metal trace with reduced RF impedance resulting from the skin effect | Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury | 2004-05-25 |
| 6723632 | Interconnect exhibiting reduced parasitic capacitance variation | — | 2004-04-20 |
| 6720624 | LVTSCR-like structure with internal emitter injection control | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2004-04-13 |
| 6717219 | High holding voltage ESD protection structure for BiCMOS technology | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2004-04-06 |
| 6707117 | Method of providing semiconductor interconnects using silicide exclusion | Vladislav Vashchenko, Philipp Lindorfer, Andy Strachon, Peter Johnson | 2004-03-16 |
| 6703710 | Dual damascene metal trace with reduced RF impedance resulting from the skin effect | Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury | 2004-03-09 |
| 6690069 | Low voltage complement ESD protection structures | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2004-02-10 |
| 6667867 | Stable BJT electrostatic discharge protection clamp | Vladislav Vashchenko | 2003-12-23 |
| 6660602 | Stand-alone triggering structure for ESD protection of high voltage CMOS | Vladislav Vashchenko, Ann Concannon, Marcel ter Beek | 2003-12-09 |
| 6660537 | Method of inducing movement of charge carriers through a semiconductor material | Philipp Lindorfer, Kyuwoon Hwang | 2003-12-09 |
| 6653716 | Varactor and method of forming a varactor with an increased linear tuning range | Vladislav Vashchenko, Pascale Francis | 2003-11-25 |
| 6645854 | Formation of a vertical junction throuph process simulation based optimization of implant doses and energies | — | 2003-11-11 |
| 6646318 | Bandgap tuned vertical color imager cell | Philipp Lindorfer | 2003-11-11 |
| 6639784 | Wedge-shaped high density capacitor and method of making the capacitor | Philipp Lindorfer, Kyuwoon Hwang, Andy Strachan, Vladislav Vashchenko | 2003-10-28 |
| 6586302 | Method of using trenching techniques to make a transistor with a floating gate | Yuri Mirgorodski, Chin-Miin Shyu, David Tsuei, Peter Johnson, Alexander H. Owens | 2003-07-01 |
| 6586317 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage | Vladislav Vashchenko, Andy Strachan | 2003-07-01 |
| 6560081 | Electrostatic discharge (ESD) protection circuit | Vladislav Vashchenko | 2003-05-06 |
| 6541801 | Triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes | Vladislav Vashchenko | 2003-04-01 |