Issued Patents All Time
Showing 226–238 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6528844 | Split-gate flash memory cell with a tip in the middle of the floating gate | Yuri Mirgorodski | 2003-03-04 |
| 6515331 | MOSFET structure for use in ESD protection devices | Manuel Carneiro | 2003-02-04 |
| 6498373 | ESD protection CMOS structure with dynamic substrate control | Vladislav Vashchenko | 2002-12-24 |
| 6492859 | Adjustable electrostatic discharge protection clamp | Vladislav Vashchenko | 2002-12-10 |
| 6433368 | LVTSCR with a holding voltage that is greater than a DC bias voltage on a to-be-protected node | Vladislav Vashchenko | 2002-08-13 |
| 6414367 | Interconnect exhibiting reduced parasitic capacitance variation | — | 2002-07-02 |
| 6407445 | MOSFET-based electrostatic discharge (ESD) protection structure with a floating heat sink | Vladislav Vashchenko | 2002-06-18 |
| 6362080 | Formation of a vertical junction through process simulation based optimization of implant doses and energies | — | 2002-03-26 |
| 6355959 | Gate electrode controllable electrostatic discharge (ESD) protection structure having a MOSFET with source and drain regions in separate wells | Vladislav Vashchenko, Manuel Carneiro | 2002-03-12 |
| 6285057 | Semiconductor device combining a MOSFET structure and a vertical-channel trench-substrate field effect device | Christoph Pichler | 2001-09-04 |
| 6121096 | Implant process utilizing as an implant mask, spacers projecting vertically beyond a patterned polysilicon gate layer | — | 2000-09-19 |
| 6103605 | Process for defining the width of silicon gates using spacers as an etch hard mask | — | 2000-08-15 |
| 5981346 | Process for forming physical gate length dependent implanted regions using dual polysilicon spacers | — | 1999-11-09 |