Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6519194 | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester | Mitsunori Tsujino, Kyoji Yamasaki | 2003-02-11 |
| 6301190 | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester | Mitsunori Tsujino, Kyoji Yamasaki | 2001-10-09 |
| 5835434 | Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire | — | 1998-11-10 |
| 5781468 | Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same | Ryuichi Matsuo, Tomohisa Wada, Shigeki Ohbayashi | 1998-07-14 |
| 5666317 | Semiconductor memory device | Susumu Tanida, Tomio Suzuki, Masanori Hayashikoshi | 1997-09-09 |
| 5663905 | Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same | Ryuichi Matsuo, Tomohisa Wada, Shigeki Ohbayashi | 1997-09-02 |
| 5574691 | Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test | Susumu Tanida, Tomio Suzuki, Masanori Hayashikoshi | 1996-11-12 |
| 5519659 | Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test | Susumu Tanida, Tomio Suzuki, Masanori Hayashikoshi | 1996-05-21 |
| 5343429 | Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein | Akio Nakayama | 1994-08-30 |
| 5315551 | Semiconductor memory device with precharging voltage level unchanged by defective memory cell | — | 1994-05-24 |
| 5111078 | Input circuit for logic circuit having node and operating method therefor | Hiroshi Miyamoto | 1992-05-05 |
| 5065365 | Semiconductor memory device carrying out reading and writing operations in order in one operating cycle and operating method therefor | — | 1991-11-12 |
| 4835743 | Semiconductor memory device performing multi-bit Serial operation | Hideto Hidaka, Kazuyasu Fujishima, Hideyuki Ozaki | 1989-05-30 |
| 4833650 | Semiconductor memory device including programmable mode selection circuitry | Hideyuki Ozaki, Kazuyasu Fujishima, Hideto Hidaka | 1989-05-23 |
| 4808844 | Semiconductor device | Hideyuki Ozaki, Kazuyasu Fujishima, Hideto Hidaka | 1989-02-28 |