Issued Patents All Time
Showing 251–275 of 302 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5550769 | Bit line structure for semiconductor memory device | Kazuyasu Fujishima, Yoshio Matsuda | 1996-08-27 |
| 5512501 | Method of manufacturing a semiconductor device having an SOI structure | Takahiro Tsuruda, Katsuhiro Suma | 1996-04-30 |
| 5513142 | Semiconductor memory device for maintaining level of signal line | Kazutami Arimoto, Shigeki Tomishima | 1996-04-30 |
| 5509132 | Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof | Yoshio Matsuda, Kazuyasu Fujishima, Mikio Asakura | 1996-04-16 |
| 5461589 | Bit line structure for semiconductor memory device with bank separation at cross-over regions | Kazuyasu Fujishima, Yoshio Matsuda | 1995-10-24 |
| 5426615 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1995-06-20 |
| 5416734 | Bit line structure for semiconductor memory device | Kazuyasu Fujishima, Yoshio Matsuda | 1995-05-16 |
| 5390140 | Signal output circuit operating stably and arrangement of power supply interconnection line therefor in semiconductor integrated circuit device | Shigeki Tomishima, Masakazu Hirose, Takahiro Tsuruda | 1995-02-14 |
| 5371714 | Method and apparatus for driving word line in block access memory | Yoshio Matsuda, Kazuyasu Fujishima | 1994-12-06 |
| 5325336 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto | 1994-06-28 |
| 5321646 | Layout of a semiconductor memory device | Shigeki Tomishima, Mikio Asakura, Kazutami Arimoto, Masanori Hayashikoshi | 1994-06-14 |
| 5321657 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazutami Arimoto, Kazuyasu Fujishima, Masaki Tsukude, Tsukasa Ohishi | 1994-06-14 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Masanori Hayashikoshi, Shinji Kawai, Mikio Asakura +4 more | 1994-05-24 |
| 5280443 | Bit line structure for semiconductor memory device | Kazuyasu Fujishima, Yoshio Matsuda | 1994-01-18 |
| RE34463 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka | 1993-11-30 |
| 5249155 | Semiconductor device incorporating internal voltage down converting circuit | Kazutami Arimoto, Mikio Asakura, Masanori Hayashikoshi, Masaki Tsukude, Shinji Kawai +1 more | 1993-09-28 |
| 5226139 | Semiconductor memory device with a built-in cache memory and operating method thereof | Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura | 1993-07-06 |
| 5222047 | Method and apparatus for driving word line in block access memory | Yoshio Matsuda, Kazuyasu Fujishima | 1993-06-22 |
| 5214601 | Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers | Kazuyasu Fujishima, Yoshio Matsuda | 1993-05-25 |
| 5179687 | Semiconductor memory device containing a cache and an operation method thereof | Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura | 1993-01-12 |
| 5103426 | Decoding circuit and method for functional block selection | Kazuyasu Fujishima, Yoshio Matsuda | 1992-04-07 |
| 5079748 | Dynamic random access memory with read-write signal of shortened duration | Hideshi Miyatake, Masaki Kumanoya, Hiroyuki Yamasaki, Yasuhiro Konishi, Yuto Ikeda | 1992-01-07 |
| 4972380 | Decoding circuit for functional block | Kazuyasu Fujishima, Yoshio Matsuda | 1990-11-20 |
| 4945517 | Dynamic random access memory | Hideshi Miyatake, Masaki Kumanoya, Hiroyuki Yamasaki | 1990-07-31 |
| 4926385 | Semiconductor memory device with cache memory addressable by block within each column | Kazuyasu Fujishima, Mikio Asakura, Yoshio Matsuda | 1990-05-15 |