Issued Patents All Time
Showing 276–300 of 302 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4922367 | Circuit for preventing latch-up of parasitic thyristor formed in CMOS integrated circuit | — | 1990-05-01 |
| 4922453 | Bit line structure of dynamic type semiconductor memory device | — | 1990-05-01 |
| 4922459 | Dynamic semiconductor memory device | — | 1990-05-01 |
| 4918692 | Automated error detection for multiple block memory array chip and correction thereof | Kazuyasu Fujishima, Yoshio Matsuda | 1990-04-17 |
| 4914630 | Refresh arrangement in a block divided memory including a plurality of shift registers | Kazuyasu Fujishima, Yoshio Matsuda | 1990-04-03 |
| 4903268 | Semiconductor memory device having on-chip error check and correction functions | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Tsutomu Yoshihara | 1990-02-20 |
| 4896297 | Circuit for generating a boosted signal for a word line | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Katsumi Dosaka, Yasuhiro Konishi | 1990-01-23 |
| 4890261 | Variable word length circuit of semiconductor memory | Kazuyasu Fujishima, Yoshio Matsuda | 1989-12-26 |
| 4843596 | Semiconductor memory device with address transition detection and timing control | Hideshi Miyatake, Masaki Kumanoya, Yasuhiro Konishi, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-06-27 |
| 4837747 | Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block | Katsumi Dosaka, Masaki Kumanoya, Hideshi Miyatake, Yasuhiro Konishi, Hiroyuki Yamasaki +3 more | 1989-06-06 |
| 4835743 | Semiconductor memory device performing multi-bit Serial operation | Kazuyasu Fujishima, Hideyuki Ozaki, Kazutoshi Hirayama | 1989-05-30 |
| 4833650 | Semiconductor memory device including programmable mode selection circuitry | Kazutoshi Hirayama, Hideyuki Ozaki, Kazuyasu Fujishima | 1989-05-23 |
| 4833654 | Method of and circuitry for generating staggered restore timing signals in block partitioned DRAM | Makoto Suwa | 1989-05-23 |
| 4823322 | Dynamic random access memory device having an improved timing arrangement | Hideshi Miyatake, Masaki Kumanoya, Yasuhiro Konishi, Katsumi Dosaka, Hiroyuki Yamasaki +3 more | 1989-04-18 |
| 4809230 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka | 1989-02-28 |
| 4808844 | Semiconductor device | Hideyuki Ozaki, Kazutoshi Hirayama, Kazuyasu Fujishima | 1989-02-28 |
| 4774691 | Semiconductor memory device | — | 1988-09-27 |
| 4760559 | Semiconductor memory device | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka | 1988-07-26 |
| 4757476 | Dummy word line driving circuit for a MOS dynamic RAM | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Tsutomu Yoshihara | 1988-07-12 |
| 4736343 | Dynamic RAM with active pull-up circuit | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasuhiro Konishi | 1988-04-05 |
| 4734890 | Dynamic RAM having full-sized dummy cell | Hideshi Miyatake, Kazuyasu Fujishima, Masaki Kumanoya, Katsumi Dosaka, Yasuhiro Konishi | 1988-03-29 |
| 4730320 | Semiconductor memory device | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Tsutomu Yoshihara | 1988-03-08 |
| 4722074 | Semiconductor storage unit with I/O bus precharging and equalization | Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Tsutomu Yoshihara | 1988-01-26 |
| 4719597 | Driving circuit for a shared sense amplifier with increased speed clock generation circuit for reading addressed memory cells | Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Katsumi Dosaka | 1988-01-12 |
| 4712123 | Dynamic memory device | Hideshi Miyatake, Kazuyasu Fujishima, Tsutomu Yoshihara, Masaki Kumanoya, Katsumi Dosaka | 1987-12-08 |