Issued Patents All Time
Showing 26–42 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5506164 | Method of manufacturing a semiconductor device having a cylindrical capacitor | Mitsuya Kinoshita, Tatsuo Okamoto, Hideaki Arima | 1996-04-09 |
| 5502324 | Composite wiring layer | Yoshinori Okumura | 1996-03-26 |
| 5489791 | Field effect transistor having impurity regions of different depths and manufacturing method thereof | Hideaki Arima, Makoto Ohi, Natsuo Ajika, Tomonori Okudaira | 1996-02-06 |
| 5448512 | Semiconductor memory device with contact region intermediate memory cell and peripheral circuit | Kazuhiro Tsukamoto, Mitsuya Kinoshita | 1995-09-05 |
| 5434439 | Dynamic random access memory having stacked type capacitor and manufacturing method therefor | Natsuo Ajika, Hideaki Arima | 1995-07-18 |
| 5408114 | Semiconductor memory device having cylindrical capacitor and manufacturing method thereof | Mitsuya Kinoshita, Tatsuo Okamoto, Hideaki Arima | 1995-04-18 |
| 5381365 | Dynamic random access memory having stacked type capacitor and manufacturing method therefor | Natsuo Ajika, Hideaki Arima | 1995-01-10 |
| 5364811 | Method of manufacturing a semiconductor memory device with multiple device forming regions | Natsuo Ajika, Hideaki Arima, Kaoru Motonami, Tomonori Okudaira | 1994-11-15 |
| 5338699 | Method of making a semiconductor integrated device having gate sidewall structure | Makoto Ohi, Hideaki Arima, Natsuo Ajika, Yasushi Matsui | 1994-08-16 |
| 5300444 | Method of manufacturing a semiconductor device having a stacked structure formed of polycrystalline silicon film and silicon oxide film | Masao Nagatomo, Ikuo Ogoh, Hideki Genjou, Yoshinori Okumura, Takayuki Matsukawa | 1994-04-05 |
| 5281838 | Semiconductor device having contact between wiring layer and impurity region | Yoshinori Okumura | 1994-01-25 |
| 5276344 | Field effect transistor having impurity regions of different depths and manufacturing method thereof | Hideaki Arima, Makoto Ohi, Natsuo Ajika, Tomonori Okudaira | 1994-01-04 |
| 5240872 | Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions | Kaoru Motonami, Natsuo Ajika, Yoshinori Okumura, Yasushi Matsui | 1993-08-31 |
| 5233212 | Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension | Makoto Ohi, Hideaki Arima, Natsuo Ajika, Yasushi Matsui | 1993-08-03 |
| 5218219 | Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region | Natsuo Ajika, Hideaki Arima, Kaoru Motonami, Tomonori Okudaira | 1993-06-08 |
| 5173752 | Semiconductor device having interconnection layer contacting source/drain regions | Kaoru Motonami, Natsuo Ajika, Yoshinori Okumura, Yasushi Matsui | 1992-12-22 |
| 5153689 | Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines | Yoshinori Okumura, Takayuki Matsukawa, Ikuo Ogoh, Masao Nagatomo, Hideki Genjo | 1992-10-06 |