Issued Patents All Time
Showing 1–25 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373111 | Monitoring memory device health according to data storage metrics | Tingjun Xie, Seungjune Jeon, Zhenming Zhou | 2025-07-29 |
| 12272418 | Performing select gate integrity checks to identify and invalidate defective blocks | Zhongguang Xu, Murong Lang | 2025-04-08 |
| 12260916 | Partial block handling in a non-volatile memory device | Zhongguang Xu, Nicola Ciocchini, Charles See Yeung Kwong, Murong Lang, Ugo Russo +1 more | 2025-03-25 |
| 12183406 | Eliminating write disturb for system metadata in a memory sub-system | Tingjun Xie, Zhenming Zhou, Charles See Yeung Kwong | 2024-12-31 |
| 12164779 | Deck based media management operations in memory devices | Zhenming Zhou, Seungjune Jeon | 2024-12-10 |
| 12050808 | Selecting a write operation mode from multiple write operation modes | Fangfang Zhu, Tingjun Xie, Jiangli Zhu | 2024-07-30 |
| 12045512 | Read refresh via signal calibration for non-volatile memories | Tingjun Xie, Zhenming Zhou, Chih-Kuo Kao | 2024-07-23 |
| 11977480 | Scaling factors for media management operations at a memory device | Mikai Chen, Murong Lang, Zhenming Zhou | 2024-05-07 |
| 11901014 | Partial block handling in a non-volatile memory device | Zhongguang Xu, Nicola Ciocchini, Charles See Yeung Kwong, Murong Lang, Ugo Russo +1 more | 2024-02-13 |
| 11894090 | Selective power-on scrub of memory units | Tingjun Xie, Zhenming Zhou | 2024-02-06 |
| 11870461 | Failure-tolerant error correction layout for memory sub-systems | Wei-Cheng Wu, Zhengang Chen | 2024-01-09 |
| 11854644 | Performing select gate integrity checks to identify and invalidate defective blocks | Zhongguang Xu, Murong Lang | 2023-12-26 |
| 11790998 | Eliminating write disturb for system metadata in a memory sub-system | Tingjun Xie, Zhenming Zhou, Charles See Yeung Kwong | 2023-10-17 |
| 11775388 | Defect detection in memory based on active monitoring of read operations | Tingjun Xie, Frederick Adi, Wei Wang, Zhenming Zhou | 2023-10-03 |
| 11776611 | Managing write disturb for units of a memory device using weighted write disturb counts | Mikai Chen, Zhenming Zhou, Murong Lang | 2023-10-03 |
| 11763896 | Preread and read threshold voltage optimization | Seungjune Jeon, Zhenming Zhou | 2023-09-19 |
| 11756597 | Power-on read demarcation voltage optimization | Mikai Chen, Murong Lang, Zhenming Zhou | 2023-09-12 |
| 11756635 | Decision for executing full-memory refresh during memory sub-system power-on stage | Tingjun Xie, Zhenming Zhou | 2023-09-12 |
| 11741008 | Disassociating memory units with a host system | Dhawal Bavishi | 2023-08-29 |
| 11720273 | Codeword error leveling for 3DXP memory devices | Jian Huang, Zhenming Zhou | 2023-08-08 |
| 11694017 | Temperature-based on board placement of memory devices | Tingjun Xie, Charles See Yeung Kwong | 2023-07-04 |
| 11693736 | Modifying conditions for memory device error corrections operations | Tingjun Xie | 2023-07-04 |
| 11688467 | Defect detection in memories with time-varying bit error rate | Zhengang Chen, Sai Krishna Mylavarapu, Tingjun Xie, Charles See Yeung Kwong | 2023-06-27 |
| 11687248 | Life time extension of memory device based on rating of individual memory units | Zhongguang Xu, Tingjun Xie, Seungjune Jeon, Murong Lang, Zhenming Zhou | 2023-06-27 |
| 11656938 | Preemptive read verification after hardware write back | Frederick Adi, Wei Wang | 2023-05-23 |