Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11915735 | Sensing scheme for a memory with shared sense components | Tae H. Kim, Scott J. Derner | 2024-02-27 |
| 11893276 | Apparatuses and methods for data management in a memory device | — | 2024-02-06 |
| 11869628 | Apparatuses and methods to perform low latency access of a memory | Daigo Toyama | 2024-01-09 |
| 11810901 | Microelectronic devices, related memory devices and electronic systems, and methods of forming microelectronic devices | Fatma Arzum Simsek-Ege | 2023-11-07 |
| 11804260 | Multiplexors under an array of memory cells | Tae H. Kim | 2023-10-31 |
| 11790980 | Driver sharing between banks or portions of banks of memory devices | George B. Raad | 2023-10-17 |
| 11783887 | Edge memory array mats with sense amplifiers | — | 2023-10-10 |
| 11777488 | Charge transfer between gate terminals of sub-threshold current reduction circuit transistors and related apparatuses and methods | Hiroshi Akamatsu, Toru Ishikawa | 2023-10-03 |
| 11751461 | Display motherboard, fabricating method and aligning method of display motherboard | Shuo Li, Ling Shi | 2023-09-05 |
| 11727980 | Apparatuses and methods for single-ended global and local input/output architecture | Luoqi Li | 2023-08-15 |
| 11715512 | Apparatuses and methods for dynamic targeted refresh steals | Liang Li, Yu Zhang | 2023-08-01 |
| 11705888 | ZQ calibration using current source | Yasuo Satoh, Hiroki Takahashi, Shuichi Tsukada | 2023-07-18 |
| 11694738 | Apparatuses and methods for multiple row hammer refresh address sequences | Masaru Morohashi, Ryo Nagoshi, Yutaka Ito | 2023-07-04 |
| 11646073 | Reference-voltage-generators within integrated assemblies | Hyunui Lee, Takamasa Suzuki, Yasuo Satoh | 2023-05-09 |
| 11587931 | Multiplexor for a semiconductor device | Fatma Arzum Simsek-Ege | 2023-02-21 |
| 11568922 | Under-memory array process edge mats with sense amplifiers | — | 2023-01-31 |
| 11551746 | Apparatuses including memory regions having different access speeds and methods for using the same | Daigo Toyama, Chikara Kondo, Takehiro Hasegawa | 2023-01-10 |
| 11550654 | Apparatus with latch correction mechanism and methods for operating the same | Jiyun Li | 2023-01-10 |
| 11544010 | Apparatuses and methods to mask write operations for a mode of operation using ECC circuitry | Ming-Bo Liu | 2023-01-03 |
| 11537306 | Cold data detector in memory system | Daigo Toyama | 2022-12-27 |
| 11538516 | Column selector architecture with edge mat optimization | Hiroshi Akamatsu | 2022-12-27 |
| 11514977 | Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods | Jongtae Kwak | 2022-11-29 |
| 11501815 | Sensing scheme for a memory with shared sense components | Tae H. Kim, Scott J. Derner | 2022-11-15 |
| 11502089 | Three-dimensional fuse architectures and related systems, methods, and apparatuses | Daigo Toyama | 2022-11-15 |
| 11495283 | Integrated assembly with memory array over base, sense amplifiers in base, and vertically-extending digit lines associated with the memory array | Beau D. Barry | 2022-11-08 |