Issued Patents All Time
Showing 25 most recent of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424297 | Error control for memory device | Nobuo Yamamoto, Donald M. Morgan, Victor Wong | 2025-09-23 |
| 11799496 | Error correction bit flipping scheme | — | 2023-10-24 |
| 11675662 | Extended error detection for a memory device | Scott E. Schaefer, Aaron P. Boehm | 2023-06-13 |
| 11514977 | Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods | Yuan He | 2022-11-29 |
| 11360848 | Error correction code scrub scheme | — | 2022-06-14 |
| 11336298 | Error correction bit flipping scheme | — | 2022-05-17 |
| 11322218 | Error control for memory device | Nobuo Yamamoto, Donald M. Morgan, Victor Wong | 2022-05-03 |
| 11314591 | Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories | Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park | 2022-04-26 |
| 11061771 | Extended error detection for a memory device | Scott E. Schaefer, Aaron P. Boehm | 2021-07-13 |
| 10951232 | Error correction bit flipping scheme | — | 2021-03-16 |
| 10860469 | Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories | Hyun Yoo Lee, Suryanarayana B. Tatapudi | 2020-12-08 |
| 10795759 | Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories | Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park | 2020-10-06 |
| 10691533 | Error correction code scrub scheme | — | 2020-06-23 |
| 10658019 | Circuit, system and method for controlling read latency | — | 2020-05-19 |
| 10534394 | Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories | Hyun Yoo Lee, Suryanarayana B. Tatapudi | 2020-01-14 |
| 10236052 | Current sense amplifiers, memory devices and methods | Onegyun Na, Seong-Hoon Lee, Hoon Choi | 2019-03-19 |
| 10090026 | Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories | Hyun Yoo Lee, Suryanarayana B. Tatapudi | 2018-10-02 |
| 9659631 | Current sense amplifiers, memory devices and methods | Onegyun Na, Seong-Hoon Lee, Hoon Choi | 2017-05-23 |
| 9571105 | System and method for an accuracy-enhanced DLL during a measure initialization mode | — | 2017-02-14 |
| 9536591 | Staggered DLL clocking on N-Detect QED to minimize clock command and delay path | — | 2017-01-03 |
| 9529379 | Timing synchronization circuit with loop counter | — | 2016-12-27 |
| 9508417 | Methods and apparatuses for controlling timing paths and latency based on a loop delay | — | 2016-11-29 |
| 9508409 | Apparatuses and methods for implementing masked write commands | Mark Kalei Hadrick, Jeffrey P. Wright, Victor Wong, Simon J. Lovett, Donald M. Morgan +3 more | 2016-11-29 |
| 9484074 | Current mode sense amplifier with load circuit for performance stability | Seong-Hoon Lee, Onegyun Na | 2016-11-01 |
| 9378791 | Apparatuses and methods for controlling a clock signal provided to a clock tree | Donald M. Morgan, Jeffrey P. Wright | 2016-06-28 |