Issued Patents All Time
Showing 25 most recent of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423010 | Memory devices with multiple sets of latencies and methods for operating the same | Dean D. Gans, Shunichi Saito, Osamu Nagashima | 2025-09-23 |
| 12394456 | Apparatuses and methods including dice latches in a semiconductor device | Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara | 2025-08-19 |
| 11914874 | Memory devices with multiple sets of latencies and methods for operating the same | Dean D. Gans, Shunichi Saito, Osamu Nagashima | 2024-02-27 |
| 11727967 | Apparatuses and methods including dice latches in a semiconductor device | Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara | 2023-08-15 |
| RE49390 | Testing a circuit in a semiconductor device | — | 2023-01-24 |
| 11335393 | Semiconductor device performing refresh operation in deep sleep mode | Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter | 2022-05-17 |
| 11314591 | Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories | Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak | 2022-04-26 |
| 11150821 | Memory devices with multiple sets of latencies and methods for operating the same | Dean D. Gans, Shunichi Saito, Osamu Nagashima | 2021-10-19 |
| 10976945 | Memory devices with multiple sets of latencies and methods for operating the same | Dean D. Gans, Shunichi Saito, Osamu Nagashima | 2021-04-13 |
| 10923171 | Semiconductor device performing refresh operation in deep sleep mode | Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter | 2021-02-16 |
| 10795759 | Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories | Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak | 2020-10-06 |
| RE47840 | Testing circuits in stacked wafers using a connected electrode in the first wafer | — | 2020-02-04 |
| 10481819 | Memory devices with multiple sets of latencies and methods for operating the same | Dean D. Gans, Shunichi Saito, Osamu Nagashima | 2019-11-19 |
| 10020045 | Partial access mode for dynamic random access memory | — | 2018-07-10 |
| 9640240 | Partial access mode for dynamic random access memory | — | 2017-05-02 |
| 9053821 | Semiconductor device performing stress test | Hiromasa Noda, Kazuki Sakuma | 2015-06-09 |
| 8988919 | Semiconductor device having a control chip stacked with a controlled chip | — | 2015-03-24 |
| 8938570 | Semiconductor device and method of manufacturing the same | — | 2015-01-20 |
| 8937488 | Calibration of impedance | — | 2015-01-20 |
| 8908411 | Semiconductor device | — | 2014-12-09 |
| 8837242 | Semiconductor device and method including redundant bit line provided to replace defective bit line | Yoshio Mizukane, Hiromasa Noda | 2014-09-16 |
| 8788738 | Semiconductor device and method of manufacturing the same | — | 2014-07-22 |
| 8760901 | Semiconductor device having a control chip stacked with a controlled chip | — | 2014-06-24 |
| 8749267 | Device | — | 2014-06-10 |
| 8737149 | Semiconductor device performing stress test | Hiromasa Noda, Kazuki Sakuma | 2014-05-27 |