Issued Patents All Time
Showing 25 most recent of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423010 | Memory devices with multiple sets of latencies and methods for operating the same | Yoshiro Riho, Shunichi Saito, Osamu Nagashima | 2025-09-23 |
| 12347521 | Time delay indication for host in memory system | Robert Nasry Hasbun, Sharookh Daruwalla | 2025-07-01 |
| 12314575 | Memory system and operations of the same | — | 2025-05-27 |
| 12308090 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Daniel C. Skinner | 2025-05-20 |
| 12265489 | Communicating data with stacked memory dies | Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright | 2025-04-01 |
| 12249969 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | — | 2025-03-11 |
| 12231106 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | — | 2025-02-18 |
| 12223998 | Apparatuses and methods for input receiver circuits and receiver masks for same | John D. Porter | 2025-02-11 |
| 12197355 | Apparatuses and methods including memory commands for semiconductor memories | Kang-Yong Kim | 2025-01-14 |
| 12183383 | Methods for row hammer mitigation and memory devices and systems employing the same | Timothy B. Cowles, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney | 2024-12-31 |
| 12184280 | Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance | — | 2024-12-31 |
| 12182397 | Apparatuses and methods for configurable memory array bank architectures | Shunichi Saito | 2024-12-31 |
| 12159660 | Methods for row hammer mitigation and memory devices and systems employing the same | — | 2024-12-03 |
| 12019570 | Apparatuses and methods including memory commands for semiconductor memories | Kang-Yong Kim | 2024-06-25 |
| 12001715 | Memory with virtual page size | — | 2024-06-04 |
| 11971820 | Variable modulation scheme for memory device access or operation | Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright | 2024-04-30 |
| 11955977 | Apparatuses and methods for duty cycle adjustment of a semiconductor device | — | 2024-04-09 |
| 11955162 | Apparatuses and methods for input receiver circuits and receiver masks for same | John D. Porter | 2024-04-09 |
| 11947412 | Methods for activity-based memory maintenance operations and memory devices and systems employing the same | — | 2024-04-02 |
| 11914874 | Memory devices with multiple sets of latencies and methods for operating the same | Yoshiro Riho, Shunichi Saito, Osamu Nagashima | 2024-02-27 |
| 11916527 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | — | 2024-02-27 |
| 11915788 | Indication in memory system or sub-system of latency associated with performing an access command | Robert Nasry Hasbun, Sharookh Daruwalla | 2024-02-27 |
| 11907546 | Memory system and operations of the same | — | 2024-02-20 |
| 11901037 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Daniel C. Skinner | 2024-02-13 |
| 11894044 | Apparatuses and methods for a multi-bit duty cycle monitor | — | 2024-02-06 |