Issued Patents All Time
Showing 51–75 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11194726 | Stacked memory dice for combined access operations | — | 2021-12-07 |
| 11189334 | Apparatuses and methods for a multi-bit duty cycle monitor | — | 2021-11-30 |
| 11152929 | Apparatuses for duty cycle adjustment of a semiconductor device | — | 2021-10-19 |
| 11150821 | Memory devices with multiple sets of latencies and methods for operating the same | Yoshiro Riho, Shunichi Saito, Osamu Nagashima | 2021-10-19 |
| 11121714 | Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance | — | 2021-09-14 |
| 11087819 | Methods for row hammer mitigation and memory devices and systems employing the same | Timothy B. Cowles, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney | 2021-08-10 |
| 11088895 | Methods and apparatuses for signal translation in a buffered memory | Timothy M. Hollis, Randon K. Richards, Bruce W. Schober | 2021-08-10 |
| 11037617 | Methods for row hammer mitigation and memory devices and systems employing the same | — | 2021-06-15 |
| 11017879 | Adjustable column address scramble using fuses | James S. Rehmeyer, Christopher G. Wieduwilt, George B. Raad, Seth A. Eichmeyer | 2021-05-25 |
| 11010092 | Prefetch signaling in memory system or sub-system | Robert Nasry Hasbun, Sharookh Daruwalla | 2021-05-18 |
| 11003388 | Prefetch signaling in memory system or sub system | Robert Nasry Hasbun, Sharookh Daruwalla | 2021-05-11 |
| 10976945 | Memory devices with multiple sets of latencies and methods for operating the same | Yoshiro Riho, Shunichi Saito, Osamu Nagashima | 2021-04-13 |
| 10978116 | Multiple concurrent modulation schemes in a memory system | Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright | 2021-04-13 |
| 10978115 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Daniel C. Skinner | 2021-04-13 |
| 10963168 | Memory system and operations of the same | — | 2021-03-30 |
| 10956333 | Prefetching data based on data transfer within a memory system | Robert Nasry Hasbun, Sharookh Daruwalla | 2021-03-23 |
| 10942854 | Prefetch management for memory | Robert Nasry Hasbun, Sharookh Daruwalla | 2021-03-09 |
| 10915474 | Apparatuses and methods including memory commands for semiconductor memories | Kang-Yong Kim | 2021-02-09 |
| 10910037 | Apparatuses and methods for input receiver circuits and receiver masks for same | John D. Porter | 2021-02-02 |
| 10904052 | Multiplexing distinct signals on a single pin of a memory device | Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright | 2021-01-26 |
| 10868519 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | — | 2020-12-15 |
| 10839874 | Indicating latency associated with a memory request in a system | Robert Nasry Hasbun, Sharookh Daruwalla | 2020-11-17 |
| 10832748 | Memory system that supports dual-mode modulation | Robert Nasry Hasbun, Timothy M. Hollis, Jeffrey P. Wright | 2020-11-10 |
| 10825485 | Apparatuses and methods for power efficient driver circuits | Timothy M. Hollis, Larren G. Weber | 2020-11-03 |
| 10796746 | Frequency synthesis for memory input-output operations | Moo Sung Chae, Daniel C. Skinner | 2020-10-06 |