JK

Jongtae Kwak

Micron: 62 patents #269 of 6,345Top 5%
NT Nanya Technology: 1 patents #447 of 775Top 60%
📍 Boise, ID: #148 of 3,546 inventorsTop 5%
🗺 Idaho: #197 of 8,810 inventorsTop 3%
Overall (All Time): #35,596 of 4,157,543Top 1%
63
Patents All Time

Issued Patents All Time

Showing 26–50 of 63 patents

Patent #TitleCo-InventorsDate
9373371 Dynamic burst length output control in a memory 2016-06-21
9128716 Memory device and control method Kallol Mazumder 2015-09-08
9087570 Apparatuses and methods for controlling a clock signal provided to a clock tree Donald M. Morgan, Jeffrey P. Wright 2015-07-21
9054675 Apparatuses and methods for adjusting a minimum forward path delay of a signal path Kallol Mazumder, Tsugio Takahashi, Yasuo Satoh 2015-06-09
9000817 Apparatuses and methods for altering a forward path delay of a signal path Kallol Mazumder 2015-04-07
8988966 Circuit, system and method for controlling read latency 2015-03-24
8947964 Current sense amplifiers, memory devices and methods Onegyun Na, Seong-Hoon Lee, Hoon Choi 2015-02-03
8928376 System and method for an accuracy-enhanced DLL during a measure initialization mode 2015-01-06
8879337 Dynamic burst length output control in a memory 2014-11-04
8878586 Seamless coarse and fine delay structure for high performance DLL Kang-Yong Kim 2014-11-04
8732509 Timing synchronization circuit with loop counter 2014-05-20
8705304 Current mode sense amplifier with passive load Seong-Hoon Lee, Onegyun Na 2014-04-22
8587354 Control of a variable delay line using line entry point to modify line power supply voltage Tyler Gomm, Kang-Yong Kim 2013-11-19
8552776 Apparatuses and methods for altering a forward path delay of a signal path Kallol Mazumder 2013-10-08
8421515 Seamless coarse and fine delay structure for high performance DLL Kang-Yong Kim 2013-04-16
8350607 System and method for an accuracy-enhanced DLL during a measure initialization mode 2013-01-08
8283961 Delay line circuit 2012-10-09
8174297 Multi-phase clock generation 2012-05-08
8093937 Seamless coarse and fine delay structure for high performance DLL Kang-Yong Kim 2012-01-10
8026747 Apparatus and method for multi-phase clock generation 2011-09-27
8018791 Circuit, system and method for controlling read latency 2011-09-13
7973577 Control of a variable delay line using line entry point to modify line power supply voltage Tyler Gomm, Kang-Yong Kim 2011-07-05
7728639 Trimmable delay locked loop circuitry with improved initialization characteristics Tyler Gomm, Eric Booth 2010-06-01
7719334 Apparatus and method for multi-phase clock generation 2010-05-18
7716510 Timing synchronization circuit with loop counter 2010-05-11